The second part of your question (2D array vs. RAM) really comes down to the resources available on your FPGA. Usually storing something as large as an image or frame of video in logic elements isn't recommended, the logic that is created during synthesis will be huge and your compiler will take an age to fit it in the FPGA if it fits at all. You should be able to get an idea of the complexity by running the first stage of compilation (in the world of Altera this is called Analysis and Synthesis) and then looking at the RTL viewer which will allow you to look at the logic graphically.
Using the RAM on your FPGA will give you a simple interface that can be driven with simple logic and this in turn will mean that the fitter will have easier time fitting it and the timing on your chip will improve.
If however you need more memory than is available then you will need to use external memory and even though there are memory controller IPs available this can be very complicated and problematic but if you need that much memory then this would still be better than implementing a huge memory array in logic.