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I am at moment trying to store an image onto an FPGA. I calculated the space required by it to be 19200 kb, and are therefor wondering whether i should store it some other way than a 2d array?.. Or does the program i create automatically store the image i create in the RAM.. And what is the benefit of storing it in the RAM...

I not quite sure why i would/should store in the ram, rather than store it as an 2d array, what benefit do i have.. It only going to be used for a look up..

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    \$\begingroup\$ Look into the Xilinx Spartan Family Guides and you will see your picture won't fit neither into distributed RAM (LUTRAM) nor into BlockRAM. You will need to use an external RAM (SRAM or DRAM) to store such a big picture. \$\endgroup\$
    – Paebbels
    Commented Dec 20, 2015 at 14:28
  • \$\begingroup\$ I am not sure.. kb => kilo bits note bytes, based on the dataseet it should be ok.. the fpga i am using is this xilinx.com/support/documentation/data_sheets/ds557.pdf \$\endgroup\$ Commented Dec 20, 2015 at 15:12
  • \$\begingroup\$ Fpga used : XC3S50AN \$\endgroup\$ Commented Dec 20, 2015 at 15:15
  • \$\begingroup\$ See Chap 4 of UG331 (Spartan-3 Generation FPGA User Guide) titled Using Block RAM. Noting 19 kb is bigger than 18 kb the next question is what word width do you need? \$\endgroup\$
    – user8352
    Commented Dec 20, 2015 at 15:36
  • \$\begingroup\$ i am not sure i understand what you mean by word width ? \$\endgroup\$ Commented Dec 20, 2015 at 16:21

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The second part of your question (2D array vs. RAM) really comes down to the resources available on your FPGA. Usually storing something as large as an image or frame of video in logic elements isn't recommended, the logic that is created during synthesis will be huge and your compiler will take an age to fit it in the FPGA if it fits at all. You should be able to get an idea of the complexity by running the first stage of compilation (in the world of Altera this is called Analysis and Synthesis) and then looking at the RTL viewer which will allow you to look at the logic graphically.

Using the RAM on your FPGA will give you a simple interface that can be driven with simple logic and this in turn will mean that the fitter will have easier time fitting it and the timing on your chip will improve.

If however you need more memory than is available then you will need to use external memory and even though there are memory controller IPs available this can be very complicated and problematic but if you need that much memory then this would still be better than implementing a huge memory array in logic.

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