I'd like to try interfacing a fast (80 MHz) ADC with a microcontroller system. The ADC (ADC12DL080) connects to a buffer flip flop (SN74LVTH162374) which then drives the MCU data pins about 6 cm away on a daughterboard. The clock output on the ADC is inverted, so I used an inverting buffer to flip the polarity and then route to the flip flops and the MCU clock input:

system layout


  1. If the MCU clock is positive triggered, then I would have a race condition depending on the propagation delays, but if it I set it to be negative triggered does it latch the D-flip flop outputs correctly?

  2. The inverted clock on the A/D is a little confusing to me. Is the idea that I should clock the flip flops have a cycle after the A/D and not using the inverter? Right now I'm relying on the delay for the buffer to let the A/D data outputs settle, which I'm not sure is a good idea. Should I move the inverter after the flip flops so that the A/D, buffer and MCU are each 1/2 cycle apart?

Edit: The MCU in this case uses the ADC clock to know when to latch in data from the data pins. It does not clock the rest of the MCU off of the clock, just the data input latch.

  • \$\begingroup\$ Are you talking about driving the MCU's system clock like this? What do you expect the MCU to do with your data on the clock edge? \$\endgroup\$ Commented Jan 15, 2021 at 17:14
  • \$\begingroup\$ @ElliotAlderson The MCU has a system clock which is already implemented. The clock input here is used to synchronize reading the data pins. It is essentially clocks the GPIO peripheral hardware. I can set it to latch data on either the rising or falling edge of the clock input. \$\endgroup\$ Commented Jan 15, 2021 at 17:47
  • \$\begingroup\$ @user - the CLK on the A/D is an input. Don't see a ~CLK. there is a DRDY, not exactly the same. assuming you're not actually sampling at 80MHz. Can a flip flop with opposite (pos/neg) edge input establish the half-cycle delay? \$\endgroup\$
    – Pete W
    Commented Jan 15, 2021 at 17:49
  • 2
    \$\begingroup\$ for future reference, including details like that will help get a good answer. yes I think DRDY can latch the FF, opposite edge of same signal can trigger GPIO. For CLK much slower than 80MHz. \$\endgroup\$
    – Pete W
    Commented Jan 15, 2021 at 17:58
  • 2
    \$\begingroup\$ Please correct your diagram to show the actual signal names for all of the components, and provide a link to the datasheet for the MCU. \$\endgroup\$ Commented Jan 15, 2021 at 18:02

1 Answer 1


The inverter between the ADC and the F/F is provided in the original application note, but I don't understand what it's there for. The ADC outputs have over 4ns of set-up time before DRDY goes high (per the ADC datasheet). The maximum setup time required by the latch is about 3.2ns. So, probably the inverter is not necessary, but it doesn't hurt anything. All that the inverter does is to vastly prolong the setup time for the latch. The inverter may act as a clock buffer, but a non-inverting buffer like 74AC125 would do the same job and still relax the set-up time constraint: it would delay DRDY, after all. Both a non-inverting buffer and the inverting 74AC04 (not ACQ - that's a typo in the datasheet) would add between 1ns and 10ns of propagation delay, so all's good - the latch's setup time specification on the data input is not violated.

The MCU can be fed the same clock as the latch, but it will need to trigger on the falling edge (opposite from the edge the latch triggers on), so that it will have enough hold time. Triggering on the rising edge would probably violate the hold time. This paragraph applies whether the buffer between the ADC and the latch CLK is inverting or not. I also presume that the MCU is using DMA to capture the data - you should check that the DMA bandwidth won't deprive the rest of your application from memory bandwidth.


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