I have implemented a dummy SPI slave device within an FPGA (Basys 3). The master device is in an MCU.
I'm trying to connect the clock signal generated by the master (MCU) to the slave clock pin (a PMOD pin in the FPGA). However, it seems that Vivado doesn't allow to provide clock signal as an input, and it stops in the implementation step. Unless I comment out this PMOD assignment, in which case it can finish the impl. step.
The error I'm getting is:
[Place 30-574] Poor placement for routing between an IO pin and BUFG. If this sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .xdc file to demote this message to a WARNING. However, the use of this override is highly discouraged. These examples can be used directly in the .xdc file to override this clock rule. < set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets JA_IBUF] > JA_IBUF_inst (IBUF.O) is locked to IOB_X1Y97 and JA_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y31
and it's caused because I'm using
JA (Pmod pin) as an input clock signal for the SPI slave device.
I know there is a number of ways of fixing this, like generating a fast clock signal within the FPGA and pass the generated MCU clock signal through an edge detector, but do I really need to do this? (I have tried this but breaks my design)
I have read that there should be some pins that are valid for routing clock signals, however I haven't found which ones are in Basys 3.
Is there any way to provide a clock signal as an input to an FPGA?
I have tried to do what the error message says, that is, adding:
set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets JA_IBUF]
to the constraints file. This works, but the error message 'highly discourages' doing it. Is there any 'good' way of doing this?