VHDL error during synthesis, declaration and syntax error

Question

use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use ieee.math_real.all;

entity dds_sine is
port(
  i_clk          : in  std_logic;
  i_rst         : in  std_logic;
  i_f          : in  std_logic_vector(31 downto 0); --frequency control word
  i_start_phase  : in  std_logic_vector(31 downto 0);
  o_sine         : out std_logic_vector(13 downto 0));
end dds_sine;

architecture rtl of dds_sine is

component counter is 
port (
  i_clk : in std_logic;
  i_rst: in std_logic;
  o_count : out std_logic_vector (31 downto 0)
  );
end component counter;

constant count_no : integer := (2**32)-1;
signal l_count : integer range 0 to count_no;

begin
    process ( i_clk , i_rst )
    begin 
      if (i_rst = '0') then
        l_count <= 0;
      elsif ( i_clk'event and i_clk = '1') then
        if (l_count = count_no) then
          l_count <= 0;
        else
          l_count <= l_count + 1;
        end if ;
      end if ;
    end process;

o_count <= l_count;

signal phase_coh : unsigned(31 downto 0);

phase_coh <= std_logic_vector(unsigned(o_count) * unsigned(i_f));

constant C_LUT_DEPTH    : integer := 2**13;  
constant C_LUT_BIT      : integer := 14;   

type t_lut_sin is array(0 to C_LUT_DEPTH-1) of std_logic_vector(C_LUT_BIT-1 downto 0);
-- generate sine value 
function init_lut_sin return t_lut_sin is
  variable v_sin_table    : t_lut_sin:=(others=>(others=>'0')); 
  variable v_tstep       : real :=0.0;
  variable v_qsine_sgn   : std_logic_vector(C_LUT_BIT-1 downto 0):=(others=>'0');
  constant c_step          : real := 1.00/real(C_LUT_DEPTH);

  begin
    for index in 0 to C_LUT_DEPTH-1 loop
      v_qsine_sgn := std_logic_vector(to_unsigned(integer(2.0**(C_LUT_BIT-1)*sin(MATH_2_PI*v_tstep)),C_LUT_BIT)); --(sin (2PI/2^n))
      v_sin_table(index)  := v_qsine_sgn;
      v_tstep := v_tstep + c_step;
   end loop;
 return v_sin_table;
 end function init_lut_sin;

constant C_LUT_SIN                 : t_lut_sin := init_lut_sin;
signal r_sync_reset                : std_logic;
signal r_start_phase               : unsigned(31 downto 0);
signal r_fcw                       : unsigned(31 downto 0);
signal r_acc                       : unsigned(31 downto 0);
signal lut_addr                    : std_logic_vector(12 downto 0);
signal lut_value                   : std_logic_vector(13 downto 0);


p_ram : process(isl_clk)
begin
  if(rising_edge(isl_clk)) then
    lut_addr   <= std_logic_vector(r_acc(31 downto 19));
    lut_value  <= C_LUT_SIN(to_integer(unsigned(lut_addr)));
  end if;
end process p_ram;

p_sine : process(isl_clk,isl_rstb)
begin
  if(isl_rstb='0') then
    oslv14_sine     <= (others=>'0');
  elsif(rising_edge(isl_clk)) then
    oslv14_sine     <= lut_value;
  end if;
end process p_sine;


end rtl;

The errors are:

1. [Synth 8-1031] o_count is not declared (line 42)
2. [Synth 8-2715] syntax error near signal [line 44]
3. [Synth 8-2715] syntax error near := [line44]
4. [Synth 8-2715] syntax error near ; [line44]
5. [Synth 8-2715] syntax error near constant [line48]
6. [Synth 8-2715] syntax error near := [line48]
7. [Synth 8-2715] syntax error near := [line49]
8. [Synth 8-2715] syntax error near ) [line51]
9. [Synth 8-1014] phase_coh is not a signal [line:46]

Answer 1

All the error messages are due to the signal o_count not being declared in this module. You need to declare a signal called o_count.

I can see that you have declared a component called counter that has a signal o_count as an output. This signal will not be automatically associated with a signal with the same name in this module.

What you need to do is instantiate your component and then connect the lower module signal with a signal in the upper module via the port map.

As an aside, I'd be very surprised if this synthesises even when you have fixed the errors. You are using the math.real package to use a Sine function. Typically the math.real package contains functions that are not part of the synthesiseable subset of VHDL.