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Problem:

We design a PCB with an JTAG compatible FPGA that I need to program.

Now I want to be able to access the JTAG Interface from either a connector (_A) or an FT2232H USB controller (_B).

The main interface would be FTDI Device while the connector should act as Backup if progamming from FTDI fails for some reason.

Question:

What is a proper way to split the signals between the connector and the USB Chip ? Or do i need to split them at all ?

I have 2 ideas so far. Maybe someone has a better idea for this ?

IDEA 1

Idea 1 split with Pin jumpers

Will this add noise or any significant quality loss to the signals ?

IDEA 2

Split signals through multiplexer / switcher IC

Looks like an elegant way to do it. My only concern is that the MUX will pull the signals that are not connected to ground via 6M Ohm internal pull down resistors (from Datasheet of the Mux). Does this affects the FTDI chip in any way ?

Thanks in advance

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  • \$\begingroup\$ You might not need to split the lines at all, if the USB chip keeps the signals in high impedance mode as long as it isn't connected via USB. \$\endgroup\$
    – sh-
    Mar 19, 2021 at 16:47

2 Answers 2

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I have successfully used a technique similar to "Idea 2" in the original post. I used Xilinx Application Note XAPP058 as a basis for the design. The diagram that follows was cut and pasted from the app note.

Diagram from XAPP-058

This should work out of the box if you are using a Xilinx device and programmer. Simple adjustments may be necessary if you are using other FPGAs or programmers. I used a common quad 2-1 mux for this (74xx157, maybe). For your case, the block shown as "Processor" would be your FT2232 chip.

A couple of notes:

Your diagram shows TDO running through the "mux/switcher". This is not needed, and will not really work with a 2:1 mux chip, as the signal path is not bidirectional. You can attach the TDO directly to both the header and the FT2232.

Also, note that the circuit shown in the Xilinx app note can use either the PGND pin on the header or a jumper (J1) to control the mux. If the PGND pin is grounded by plugging in the programmer, or the jumper is shorted, the mux select pin will be pulled to ground to connect the FPGA to the programmer. (If left floating, the select input is pulled high with the attached pullup resistor.)

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    \$\begingroup\$ Used with a 74AVC4T774, you can have bidirectional level shifting as well (tie /OE to PGND, through an inverter or not depending on wiring). There is a variation of XAPP058 schematic in DS593, figure 16, p. 17. The PGND pin also exists under name "GNDDetect" (pin 9) on 10-pin "cortex" headers that are quite common for JTAG adapters today as well. \$\endgroup\$
    – Nipo
    Mar 30, 2021 at 13:17
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Have a look at the Xilinx development boards - some of them support both an onboard USB-JTAG and a header.

Generally, the bridge chip will leave the lines in high-Z when it’s not active. So you don’t need to mux them, just add the header.

You will want to add pull-ups to TMS, TCK and TDI to improve noise tolerance. You’ll see those on the Xilinx boards.

That said, what I do instead is just have a 6-pin header and use an external JTAG adapter. Some of my boards are very small (e.g., M.2) and I can’t abide the space or the cost of the FTDI chip.

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