In Weste and Harris's CMOS VLSI Design, they write
In Section 10.2.5 we will see that flip-flops may experience hold-time failures if the system has too much clock skew, i.e., if one flip-flop triggers early and another triggers late because of variations in clock arrival times. In industrial designs, a great deal of effort is devoted to timing simulations to catch hold-time problems. When design time is more important (e.g., in class projects), hold-time problems can be avoided altogether by distributing a two-phase nonoverlapping clock. Figure 1.33 shows the flip-flop clocked with two nonoverlapping phases. As long as the phases never overlap, at least one latch will be opaque at any given time and hold-time problems cannot occur.
Figure 1.33 is given below, and it's simply a D flip-flop implemented in a master-slave configuration (and this time with nonoverlapping clock phases):
I am confused about two things:
(1) Is the point about hold-time violations with respect to the internal latches within the same flip flop, or to different flip-flops in the larger digital system? That is, is there an issue with the standard master-slave configuration as below, in that it might misfire in going CLK-to-Q if we use the standard single-clock implementation?
NB that in the image below the complemented QM signal (output of master latch) is an error (I believe) but that is immaterial to the question.
(2) I suspect the answer to my (1) above is that the comment was with regard to hold-time violations in different flip-flops and, if so, I do not understand how the nonoverlapping nature of the clock phases helps us avoid all possible hold time problems, as claimed. Let's consider two flip-flops, F1 and F2, built as in the first picture. Is the point that F1 only launches when \$\phi_1\$ goes high so that if we pick the non-overlap time \$t_{overlap}\$ long enough then we'll have no hold time violation with F2 receiving this launch? F2 needs its D2 input stable for some hold time around the falling edge of \$\phi_2\$ but I can't quite see past this. Would an answerer be able to explain, for instance, a situation in which these two-phase flip flops don't have an issue but the standard single-phase flip-flops do?
