Error while building a MIPS ALU Controller Design

Question

// ============================================================
// S23_ALU_control_tb.v
//
// Testbench for MIPS ALU Control Unit
// ====================================

`timescale 1ns / 1ps

module test_ALU_CTL;

   parameter finishtime = 100;

   module ALU_control (
    output reg [3:0] ALUctl,
    input [1:0] ALUOp,
    input [5:0] funct
   );

   always @(*)
   begin
       case ({ALUOp, funct})
           6'b00_000000: ALUctl = 4'b0010;   // lw
           6'b01_000000: ALUctl = 4'b0110;   // beq
           6'b10_000000:                     // R-type
               case (funct)
                   6'b100000: ALUctl = 4'b0010;   // add
                   6'b100010: ALUctl = 4'b0110;   // sub
                   6'b100100: ALUctl = 4'b0000;   // and
                   6'b100101: ALUctl = 4'b0001;   // or
                   6'b101010: ALUctl = 4'b0111;   // slt
                   6'b100111: ALUctl = 4'b1100;   // nor
                   6'b100110: ALUctl = 4'b1101;   // xor
                   default: ALUctl = 4'b1111;      // default value
               endcase
           default: ALUctl = 4'b1111;      // default value
       endcase
   end

  initial $monitor($time, " ALUOp=%b funct=%b ALUctl=%b",
                    ALUOp, funct, ALUctl);

endmodule // ALU_control

When I run the code I get the below error:

TOOL:   xmverilog   23.09-s004: Started on Apr 16, 2024 at 23:04:20 CDT
TOOL:   xmverilog   23.09-s004: Started on Apr 16, 2024 at 23:04:20 CDT
xmverilog(64): 23.09-s004: (c) Copyright 1995-2023 Cadence Design Systems, Inc.
file: S23_ALU_control_tb-33.v
   module ALU_control (
        |
xmvlog: *E,EXPENM (S23_ALU_control_tb-33.v,13|8): expecting the keyword 'endmodule' [12.1(IEEE)].
    module worklib.test_ALU_CTL:v
        errors: 1, warnings: 0
           6'b00_000000: ALUctl = 4'b0010;   // lw
                      |
xmvlog: *W,INTOVF (S23_ALU_control_tb-33.v,22|22): bit overflow during conversion from text [2.5(IEEE)] (6 bits).
           6'b01_000000: ALUctl = 4'b0110;   // beq
                      |
xmvlog: *W,INTOVF (S23_ALU_control_tb-33.v,23|22): bit overflow during conversion from text [2.5(IEEE)] (6 bits).
           6'b10_000000:                     // R-type
                      |
xmvlog: *W,INTOVF (S23_ALU_control_tb-33.v,24|22): bit overflow during conversion from text [2.5(IEEE)] (6 bits).
    module worklib.ALU_control:v
        errors: 0, warnings: 3
xmverilog: *E,VLGERR: An error occurred during parsing.  Review the log file for errors with the code *E and fix those identified problems to proceed.  Exiting with code (status 1).
TOOL:   xmverilog   23.09-s004: Exiting on Apr 16, 2024 at 23:04:21 CDT  (total: 00:00:01)

I am new to Verilog. Can anyone explain these errors?

Answer 1

The error message (*E) occurs because you should create 2 separate modules, not one inside another. Then you should place an instance of the design module inside the testbench module. Here is one way to do so:

`timescale 1ns / 1ps

module ALU_control (
 output reg [3:0] ALUctl,
 input [1:0] ALUOp,
 input [5:0] funct
);

   always @(*)
   begin
       case ({ALUOp, funct})
           6'b00_000000: ALUctl = 4'b0010;   // lw
           6'b01_000000: ALUctl = 4'b0110;   // beq
           6'b10_000000:                     // R-type
               case (funct)
                   6'b100000: ALUctl = 4'b0010;   // add
                   6'b100010: ALUctl = 4'b0110;   // sub
                   6'b100100: ALUctl = 4'b0000;   // and
                   6'b100101: ALUctl = 4'b0001;   // or
                   6'b101010: ALUctl = 4'b0111;   // slt
                   6'b100111: ALUctl = 4'b1100;   // nor
                   6'b100110: ALUctl = 4'b1101;   // xor
                   default: ALUctl = 4'b1111;      // default value
               endcase
           default: ALUctl = 4'b1111;      // default value
       endcase
   end

  initial $monitor($time, " ALUOp=%b funct=%b ALUctl=%b",
                    ALUOp, funct, ALUctl);

endmodule // ALU_control

module test_ALU_CTL;
    parameter finishtime = 100;
    reg [1:0] ALUOp;
    reg [5:0] funct;
    wire [3:0] ALUctl;

ALU_control dut (
    .ALUOp   (ALUOp),
    .funct   (funct),
    .ALUctl  (ALUctl)
);
endmodule

Refer to How to instantiate a module.

The warning messages (*W) are self-evident. The constant (6'b10_000000) has 8 bits to the right of the b, but you specified a bit width of 6 to the left of the b. To specify a width of 8, use:

8'b10_000000

Making those changes allows the code to compile without errors or warnings.