Does a clock cycle (period) start 'high' or 'low'?

Question

I'm familiar with what a clock cycle is and its purpose, but I'm wondering if is there any standard convention as to whether a clock cycle (period) starts high and then transitions low or if it starts low and then transitions high (assumming a square waveform) or if it differs from one manufacturer to another. Likewise if it does differ, is one more common that the other.

I have seen some diagrams that start clock cycles 'high' and others that start 'low' but I haven't seen this point explicitly addressed in text before hence the question.

I ask the question in the context of flip-flop circuits specifically. With a low-to-high clock cycle period, I'm assuming that a positive edge triggered flip-flop would store a value at the mid-point of a cycle, whereas in the case of a high-to-low clock cycle period, a positive-edge triggered flip-flop would store a value at the start of a cycle.

Answer 1

It can be defined in any way you want depending on what is relevant.

For a pure clock it does not matter.

For a circuit that is sensitive to rising or falling edge, you are free to define if a clock cycle is from rising to rising edge or from falling to falling edge.

Answer 2

Some communication protocols allow a clock cycle to be configured to be started as either 'low' or 'high'. E.g. for Serial peripheral interface (SPI) this is selected by CPOL.

Introduction to SPI Interface has the following in Table 1. SPI Modes with CPOL and CPHA:

SPI Mode	CPOL	CPHA	Clock Polarity in Idle State	Clock Phase Used to Sample and/or Shift the Data
0	0	0	Logic low	Data sampled on rising edge and shifted out on the falling edge
1	0	1	Logic low	Data sampled on the falling edge and shifted out on the rising edge
2	1	0	Logic high	Data sampled on the falling edge and shifted out on the rising edge
3	1	1	Logic high	Data sampled on the rising edge and shifted out on the falling edge

The Analog Devices article linked above has timing diagrams for each of the SPI modes.

Also, CPHA allows the clock edge used to sample data / shift data out to be changed. This is somewhat related to the other question Advantages/disadvantages and use cases for positive and negative edge-triggered flip-flops, in that shows a hardware design may allow the the meaning of clock edges to be selected by software rather than being fixed. A datasheet for a SPI controller in a microcontroller will typically have registers which allow the SPI mode used to be selected.

I'm not sure of the history behind SPI being defined with the four different modes.