Consider a positive edge triggered D flip flop with input signal X with a setup time of 20 ns and a hold time of 0 ns. What will be the output?

C is clock signal with a period of 40 ns.

Enter image description here

During the 6th positive edge, we see that the data (or X) is not stable for 20 ns (setup time) before it as it goes from 1 to 0. So the output is not predictable, right?

When I asked this to my professor, he said that the output of the flip flop would be the value of the input (X) before 20 ns which is 1 here.

Is he correct?


5 Answers 5


If the flip-flop's setup time is 20 ns, it means that data has to be stable atleast 20ns before the capturing clock-edge. Similarly hold time is the amount of time, data has to remain stable after a clock edge has appeared. So together they define a "setup-hold-window", in which data has to remain stable.

enter image description here If the data changes/toggles within this window, the output is unpredictable or metastable.

In your question data toggles within the setup window prior to the 6th clock edge, means the output is unpredictable.

  • \$\begingroup\$ Maybe you can correct your professor tomo. \$\endgroup\$
    – Mitu Raj
    Commented Dec 31, 2017 at 15:32
  • 8
    \$\begingroup\$ And it's worth mentioning that, depending on internal delays, hold times can be negative. That is, for some ICs you can actually release the data before the clock edge arrives. But there remains a window in which the data must be stable. \$\endgroup\$ Commented Dec 31, 2017 at 16:24
  • 1
    \$\begingroup\$ Minor correction: On modern processes true metastability only happens in a window that is on the order of femtoseconds. The vast, vast majority of cases where setup/hold is violated you will not see metastability. The result in these cases will actually be deterministic but highly dependent on temperature in addition to the inputs. I still wouldn't agree with the professor and I'd agree with you that the output is unpredictable for all intents and purposes, but metastability is not the issue (and in fact is rarely ever the issue). \$\endgroup\$
    – jalalipop
    Commented Jan 2, 2018 at 13:05

Your professor needs to cut back on the herbs.

Since the data is changing within the setup time, and since setup time is a minimum amount of time before the clock that the data needs to be stable, it is impossible to tell whether the output will be a zero or a one. In fact it could even enter a metastable state and oscillate.


If the data is stable between the setup and hold times, then the D latch manufacturer is guaranteeing that the output of the D latch will be predictable, what it says it will be in the data sheet.

If the data changes during the setup to hold window, then it's likely that the output will be a solid 0 or 1, but the manufacturer makes no assertion as to which.

It's only likely to be a solid 0 or 1, it's not guaranteed. The output could go metastable. This means there could be a finite and unpredictable extra time, beyond the normal propagation delay quoted in the data sheet, for which two gates driven by this output could make different decisions about whether it was a 0 or 1. This is a Bad Thing.


The output will be unknown and a simulator will reflect this by setting the output value to 'X'.


If the input meets the setup and hold time requirements, then the output is essentially "guanranteed" to reflect the input; if it violates the setup time, the behavior is no longer guaranteed or fully predictable, as you say.

Your professor may be "kind of probably" right in the sense that he may be expressing what the output signal is quite likely to end up being, especially if he is interpreting the setup time as being a deterministic description of the flip-flop's behavior, rather than a minimum requirement with possible variation from one set of conditions to the next. But your interpretation and instincts are really on target. Setup and hold times are generally used to express min/max values for which the behavior can be reliably predicted across process/voltage/temperature variations, and whenever the input violates them, the output cannot be reliably predicted.

If the flip-flop generally has up to 20ns of delay from the input to where the clock edge takes effect, then the output is most likely to end up being what the input was "around" (up to) 20ns before the clock edge, as your professor suggests. But the only thing that is specified for the device is that if the setup and hold times are met, then the output will follow the input.

So I guess in other words you may both be right to a degree, but your interpretation is 100% right, while your professor's answer is only "probably" right, and the degree to which his answer will be right is - as you say - unpredictable.

(And of course in a practical - rather than academic - sense you would only use that answer in a design where it was acceptable to have the output in that clock cycle be "probably 1" without any specification of how likely that was, or where there were no real consequences for potentially having the flip-flop enter a metastable state "for a while". Those applications tend to be more rare.)


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