In given this circuit, how can you calculate the minimum cycle time, in order that the circuit will work properly? I need you to explain to me how to relate to Delays?

enter image description here

It must be something with this formula? Tclk>= Tpd (FF1) + Tpd (CL) + Tsetup (FF2) if yes,How to combine the "Delay" here?

In addition to the first example, I thought about another case. To try to understand the formula, adding another flip-flop. I am not so sure how to approach in case of : FF2 -> FF3, FF3 -> FF2, and: FF3 -> FF1. Can you help me? enter image description here

This is correct (?):
Tper12+Tdelay1[min] ≥ Tpd(FF1)+Tpd(CL1)+Tsetup(FF2)
Tper23+Tdelay2[min]-Tdelay1[max] ≥ Tpd(FF2)+Tpd(CL2)+Tsetup(FF3)
Tper31-Tdelay1[max]-Tdelay2[max] ≥ Tpd(FF3) + Tpd(CL3) + Tsetup(FF1)

  • \$\begingroup\$ You have a circuit with just 7 nodes. Draw the timing diagram that shows when each of those nodes has a valid value. There are two paths you need to consider: FF1-->CL1-->FF2 and FF2-->CL2-->FF1. Since the two FFs have different clocks, you need to explicitly show that relationship as well. One of these will need a longer clock period than the other, and this will determine the minimum clock period of the whole thing. \$\endgroup\$
    – Dave Tweed
    Commented Aug 14, 2016 at 14:35
  • \$\begingroup\$ Can you please explain me hwo to calculate: FF2-->CL2-->FF1? I'm trying to do this for two days... \$\endgroup\$
    – Mathmatic
    Commented Aug 14, 2016 at 14:37
  • \$\begingroup\$ Start with this: What can you say about the relationship between the two FF clocks? \$\endgroup\$
    – Dave Tweed
    Commented Aug 14, 2016 at 14:38
  • \$\begingroup\$ I know this: Tclk>=Tpd(FF2)+Tpd(CL2)+Tsetup(FF1). But what with the delays? \$\endgroup\$
    – Mathmatic
    Commented Aug 14, 2016 at 14:39
  • \$\begingroup\$ No, that formula works only if the two FFs have the same clock. In this case, they don't. What can you say about the clocks? \$\endgroup\$
    – Dave Tweed
    Commented Aug 14, 2016 at 14:41

1 Answer 1


Since this is a "homework" question, I'll only give a partial answer. You seem to be stuck on how to handle the fact that the two FFs have different clocks.

The two FFs are driven by clocks that have two different delays from a common clock. Start by drawing a timing diagram:

           reference time
              |________________                  ________________
Clock     ____/                \________________/                \_________
           -->| |<-- Delay1(min)
           -->| |  |<--Delay1(max)
              | |__|________________               ___________________
Clk(FF1)  ____|_/__/             \__\_____________/__/             \__\____
           -->|  |<-- Delay2(min)
           -->|  |   |<--Delay2(max)
                 |___|_________________             _____________________
Clk(FF2)  _______/___/             \___\___________/___/             \___\_

As you can see, there is a considerable amount of potential clock skew between the two clocks.

You have to consider two extreme cases:

  • Delay1 has its minimum value and Delay2 has its maximum value
  • Delay1 has its maximum value and Delay2 has its minimum value

It can be easier if you use one of the FF clocks as the reference, which allows you to show the total skew between the two FFs directly. Here's what you get when you use Clk(FF1) as the reference:

              reference time
                 |________________                  ________________
Clk(FF1)  _______/                \________________/                \______
            -->| |<-- Delay1(min)
         -->|  | |<--Delay1(max)
            |__|_|______________               ___________________
Clock     __/__/ |           \__\_____________/__/             \__\________
            |  | |
         -->|  |<-- Delay2(min)
            -->| |    |<--Delay2(max)
               |_|____|________________            _______________________
Clk(FF2)  _____/_|____/         \______\__________/______/          \_____\
                 |                                |
                 |<------ total path delay ------>|
                          from FF1 to FF2

Note that we show the minimum value of Delay2 relative to the earliest possible Clock edge, while we show the maximum value relative to the latest possible edge. This demonstrates that the total skew between the two FF clocks is equal to the sum of the skews (differences between min and max delays) for Delay1 and Delay2.

When considering the combinatorial path from FF1 to FF2, you need to account for the fact that the FF2 clock can occur Delay2(min)-Delay1(max) relative to the FF1 clock at the earliest, and your setup time for FF2 must be relative to that point in time. There is a corresponding relationship when considering the path from FF2 to FF1.

I hope this is enough to get you going.

Since you still seem to be stuck, here's more:

The general rule is that when considering the FF1→CL1→FF2 path, the clock at FF2 cannot come any earlier than the sum of the maximum delays starting with the clock at FF1, including the clock-to-out delay of FF1 and the setup time of FF2. The stuff I talked about above shows how to that total path delay relates to the clock period with the two delays.

When the clocks are identical, you can say:

Tper(min) ≥ TpdFF1(max) + TpdCL1(max) + TsuFF2(max)

When they are not, you need to use the more general formula:

Tclk(FF2) - Tclk(FF1) ≥ TpdFF1(max) + TpdCL1(max) + TsuFF2(max)

Knowing that the earliest Tclk(FF2) is:

Tclk(FF2) - Tclk(FF1) = Tper12(min) - Delay1(max) + Delay2(min)

You can combine these together to get:

Tper12(min) ≥ TpdFF1(max) + TpdCL1(max) + TsuFF2(max) + Delay1(max) - Delay2(min)

Similarly, when you consider the FF2→CL2→FF1 path, you get a similar formula:

Tper21(min) ≥ TpdFF2(max) + TpdCL2(max) + TsuFF1(max) + Delay2(max) - Delay1(min)

The final answer will be the larger of these two values.

  • \$\begingroup\$ Did you create those timing diagrams by hand? \$\endgroup\$
    – jbord39
    Commented Aug 14, 2016 at 15:28
  • \$\begingroup\$ @jbord39: Yes. Doing it in ASCII was simpler than firing up a drawing tool. I'm used to doing it from back in the days when I had to do all of my documentation in ASCII. \$\endgroup\$
    – Dave Tweed
    Commented Aug 14, 2016 at 15:29
  • \$\begingroup\$ This is not about homework, I try to understand in general how the "delay", entered the formula of the cycle time? I know to draw the diagram. I ask only about the formula. And I'm trying to understand how the formula should be, and it still is not clear from the diagram. There is no general formula in case of delay? (I brought this case just an example out of my head. Only to realize through this example what should be the formula.) \$\endgroup\$
    – Mathmatic
    Commented Aug 14, 2016 at 17:16
  • \$\begingroup\$ That's why I put "homework" in quotes. Regardless of where the problem actually came from, the point is to help you work out the solution on your own, not to hand it to you on a silver platter. \$\endgroup\$
    – Dave Tweed
    Commented Aug 14, 2016 at 17:37
  • 1
    \$\begingroup\$ It follows from the timing diagrams. Really, I don't know how to make this any simpler. \$\endgroup\$
    – Dave Tweed
    Commented Aug 14, 2016 at 18:46

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