Implementing a Mealy Machine in Verilog

Question

I have a piece of code that I don't understand:

always_ff @(posedge CLK)
state <= RST || ~A[0]===1'bx || ~A[1]===1'bx ? 0 : nextstate;

A is the input. What is this piece of code exactly doing? What is ~A[0]===1'bx or ~A[1]===1'bx?

My guess is that this code is checking if either one of the inputs aren't valid (1'bx). If one of the inputs aren't valid, we jump back to the starting state 0.

But why the negation in ~A[0]===1'bx?

Answer 1

I assume this is a shortcut for:

A[0]===1'bx || A[0]===1'bz

If A[0] is 1'bx, ~A[0] will still be 1'bx.
If A[0] is 1'bz, ~A[0] will make it 1'bx.

I have to assume this is in a test bench because that code can not be synthesized.

A more meaningful way to write the code is:

state <= RST || $isunknown(A[1:0]) ? 0 : nextstate;