I read in the lecture slides to a VLSI course that clock gating also can lead to a decreased chip area size. In my understanding, clock gating decreases the chip size as this technique requires an additional FF + and gate.

up vote 3 down vote accepted

If there is no clock gating a feed-back MUX is used to keep the output the same if the enable is low. One for every FF.

With clock gating they can all be replaced with an AND gate.

Additionally clock gating means lower power which means a leaner, smaller power grid.

The diagram below is an illustration of the difference.

I don't know where your "additional FF" comes from.


simulate this circuit – Schematic created using CircuitLab

Your Answer

By clicking "Post Your Answer", you acknowledge that you have read our updated terms of service, privacy policy and cookie policy, and that your continued use of the website is subject to these policies.

Not the answer you're looking for? Browse other questions tagged or ask your own question.