A schematic by Lattice Semiconductor includes the diagrammed D flip-flop. This D flip/flop accepts, among others, a Set/Reset signal.

I would have understood a Set signal. I would have understood a Reset signal. I would even have understood Set and Reset signals on separate lines. I cannot, however, understand a joint Set/Reset signal.

  |                 |
--| D             Q |--
--|>CLOCK           |
  |                 |
  |    SET/RESET    |


What is a Set/Reset signal, please?


For optional reference, here is the data sheet (1.5 MB) in which the D flip-flop appears, in Figure 3.2, page 9. I do not, of course, ask you to go to read a 52-page data sheet for me! (That would be my homework, not yours.) Therefore, the relevant quotes from the data sheet as far as I know are as follows.

Each logic cell includes ... a D-style flip-flop (DFF), with an optional clock-enable and reset control input.... [Sect. 3.1.1, page 9.]

... Signal description [is as follows].

  • Function: input.
  • Type: control signal.
  • Signal name: Set/Reset. (Footnote: if Set/Reset is not used, then the flip-flop is never set/reset, except when cleared immediately after configuration).
  • Description: Asynchronous or synchronous local set/reset shared by [a block of eight logic cells, each cell including a flip-flop]. [Table 3.1, page 10.]

One can externally disable the Set/Reset signal, presumably via multiplexing or high-Z pull-down, but I see nothing to decide whether the Set/Reset signal—when not disabled—should set the flip-flop or reset it.

Am I missing something?

If you know what a Set/Reset signal is, would you tell me?


In addition to @Tom Carpenter's excellent answer, we have another way to verify that this interpretation is indeed correct.

Project IceStorm provides complete documentation of the bits that configure the LOGIC Tile. In particular:

LC_i[18] is the Set_NoReset bit. When this bit is set then the set/reset signal will set, not reset the flip-flop.

We can also see that the Flipflop can also be configured as a latch.


In all likelihood it isn't really a "set/reset" signal, so much as a signal that can be configured to be either set or reset depending on how the device is configured. Note that in figure 3.2 (copied below for clarity), it says "flip-flop with optional [...] set or reset controls".

Similarly it will also be the configuration bits that disable the signal entirely if unused. You can see this in figure 3.2:

Fig 3.2

  • \$\begingroup\$ Hm. Yes, your interpretation makes sense, but if you are right, then the schematic might have been more clearly drawn. They might have just added an XOR gate. Then it would have been clear. Therefore, your interpretation is helpful. I appreciate it. \$\endgroup\$ – thb Nov 22 '18 at 20:01
  • 4
    \$\begingroup\$ Since we have complete bitstream documentation for this FPGA, we can see further evidence that this interpretation is correct: “LC_i[18] is the Set_NoReset bit. When this bit is set then the set/reset signal will set, not reset the flip-flop.” \$\endgroup\$ – wrtlprnft Nov 22 '18 at 21:31
  • \$\begingroup\$ @wrtlprnft: if your comment were an answer, then I should be glad to upvote it. (Incidentally, Icestorm is precisely what I am trying to get up and running, so your hyperlink is most appropriate.) \$\endgroup\$ – thb Nov 22 '18 at 22:26
  • \$\begingroup\$ Note that an XOR gate may change the polarity of the signal. But it will not change the functionality from RESET to SET or vice versa. \$\endgroup\$ – Oldfart Nov 23 '18 at 14:18

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