Why do we need NMOS transistors for NAND gate?

Question

I have a hard time understanding how gates are built from CMOS transistors. For example, I don't understand why do we need the NMOS transistors if the PMOS transistors will already produce the desired outputs?

if X or Y on both PMOS transistors is 0 , then both transistors will be open and the output will be 0 because there will be no flow of the current

if one of the inputs X or Y will be 1 , then one of the switches will be open and there will be current flow, so the output will be 1.

it is only when both X and Y are 1 the current wont flow.

so, why do I need the NMOS transistors at the bottom then???

Answer 1

if X or Y on both PMOS transistors is 0 , then both transistors will be open and the output will be 0 because there will be no flow of the current.

The output will not be '0', it will be floating.

• That will leave any connected devices with a floating input and very susceptible to noise.
• The connected devices also have input capacitance and these need to be discharged to drive the inputs to logic 0.
• For high-speed logic the inputs must be switched quickly. The way to do this is to pull high and pull low directly.

Figure 1. Note that if we leave X and Y floating that it may be possible for the inputs to float to a stage where both the NMOS and PMOS transistors are partially on resulting in "shoot-through". In this state enough current passes through the devices and they heat up and can burn out.

Answer 2

You make the common, and mistaken, assumption that a node that is not actively driven (has zero current flowing) must be at a low voltage. That is not true.

The output of the gate must be pulled down or it can not operate reliably. Without a pull down of some kind the output voltage is indeterminate. You could use a resistor pulldown but that will waste a lot of power and/or be slower than an NMOS pulldown.

Answer 3

An NMOS transistor acts as a very low resistance between the output and the negative supply when its input is high. Here when X and Y are high, the two seried NMOS becoming just like wires will force the output to be low (FALSE).

In all 3 other cases the upper transistors, one or both, will force the output to be high (TRUE). If the NMOS transistors were missing, the output would just be floating like an antenna, hence capturing any parasitic signals and limiting the operational bandwidth.

Moreover that bandwidth could further be reduced because of the natural capacity of the circuit boards, or even semiconductor wafers used to build the system. Forcing the output to "low" would discharge immediately this capacity charged during "high" period.

Answer 4

You've received some good answers and I agree that the currently selected best answer should be the best answer, but I wanted to add some insight.

When we call an undriven node "floating" we do it for one very good reason. Electrical nodes (wires) capacitively and inductively couple charge from all over the place. The basic principle is why motors and generators do what they do: charge is coupled between the rotor and stator windings. In motors and generators, this is desirable. In the world of microelectronics, we call this undesirable effect crosstalk.

Crosstalk is coupled from everywhere: other nearby nodes including signal nodes (wires used to transmit data) and clock nodes (evil little badgers when it comes to crosstalk), the power plane, the ground plane, and the substrate. Capacitive and inductive modeling for very high speed signal paths is detailed (bordering on enormous) literally for this one reason alone. Not-cutting-edge designs often only focus on the capacitive element because the wire lengths aren't long enough for the inductive element to matter as much and, as a result, simulation time is greatly reduced. Really-not-cutting-edge designs often lump capacitances together to further speed up the simulations.

My point is, without doing something to guarantee a signal node will be driven high AND low, the node's voltage will bounce all over the place. In the designs I worked on, it wasn't uncommon for the voltage to jiggle around 75% of Vcc simply because no insulator (including your substrate) is perfect. This is a frankly massive problem as the 75% transition point is usually within the metastable region of CMOS operation (the region where the circuit doesn't quite know whether it wants to be high or low, meaning it's moderately resistive and sensitive to crosstalk).

For completeness, consider that one pair or the other of your MOS transistors can be replaced with a single resistor (depending on which pair you pick, connected to Vcc or Gnd). This will work great so long as the ratio between the MOS on-resistance and the resistor is enough to allow the signal voltage to clear the gate-off voltage, but it will be power-hungry and slow. (In some of my old designs a very small NMOS transistor would be gate-to-drain connected to make it a resistive diode. We'd use this in reset circuits where the occasional pulse to reset something was so rare that the higher power loss and slower speed weren't an issue compared to the space savings of a full CMOS setup.)

My own background (from 30 years ago) was (is...) in BiCMOS design. Conceptually, a simple inverter was a 3-inverter device. The first CMOS inverter was very small. It drove a larger CMOS inverter, which then drove a Bipolar transistor array that had very, very small parallel CMOS devices. The result was a device that could drive an enormous amount of energy. (Usually data backplanes.) The technology was spectacularly good for 1V solutions on satellites.

But if you think about it, that means you have the traditional diode voltage drop. That's why we used the parallel CMOS devices, to guarantee full transition rather than a partial transition.

To summarize, when designing in a digital world, you want (a) full control over every data node and (b) as much control over capacitive and inductive coupling as possible. (A) is more important than (b) because you can't completely control (b).

Answer 5

We can also use Pseudo-NMOS Logic, where we can use a single NMOS transistor in the pull-down network with the gate input of the NMOS transistor tied to GND. This would be slower than CMOS logic for NAND gates but it would have the same speed for NOR gates.

Answer 6

Your question is conceptual; so it can be answered by the help of well-known simple electrical concepts as voltage divider, potentiometer, rheostat...

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Logic gates, like most digital and analog circuits, are devices with voltage inputs and outputs, ie, they are voltage-controlled voltage sources. Their output stages are implemented as voltage-controlled voltage dividers consisting of two elements in series. One of them (pull up) is connected to Vdd and the other (pull down) is grounded.

The main property of these "pulling" elements is resistance. But while in the simple resistor voltage divider their resistance is linear, in the output stages of electronic circuits it is nonlinear (dynamic); this causes them to switch quickly.

The output voltage of this voltage divider configuration is controlled by changing the resistance of one, the other or both elements (in opposite directions). For this purpose, they are implemented by transistors (MOSFET, BJT, etc.).

The output stage could be implemented by only one controlled element (transistor) connected to one of the supply rails only if a load with relatively low resistance is connected to the other rail. This configuration is called "open drain (collector)". Actually, the transistor and load constitute a voltage divider as above... but this is not the case here...

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So, according to simple electrical concepts, in the case of a low-impedance load, we cannot change the output voltage with only one resistor (PMOSFET in your circuit) connected in series to the supply rail since there is no current flowing through and voltage drop across the resistor. We need another resistor (NMOSFET) connected to ground to provide a current and voltage drop across the upper PMOSFET.

The load can serve as such a resistor if it has relatively low resistance. If not, we have to connect another resistor to ground, in order to close the circuit.