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Results tagged with verilog
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user 251683
Verilog is a hardware description language (HDL) used to model electronic systems. It is most commonly used in the design, verification, and implementation of digital logic chips. Please also tag with [fpga], [asic] or [verification] as applicable. Answers to many Verilog questions are target specific.
2
votes
1
answer
259
views
Synthesizing error while designing 4-bit ALU in Verilog
I'm trying to design a 4-bit ALU which does the following functions:
I've written the below Verilog code, and the simulation is working fine without any errors. …
- 9,763
3
votes
1
answer
4k
views
Error: HDL Compiler : 1660 : Procedural assignment to a non-register big_mant is not permitt...
In the lines wherever I try to do the assignment of value, the above error pops up. Please tell me what's the mistake and guide me with the corrected code snippet.
`timescale 1ns / 1ps
module big_sm …
- 1
5
votes
2
answers
15k
views
'1011' Overlapping (Moore) Sequence Detector in Verilog
I'm designing a "1011" overlapping sequence detector, using Moore Model in Verilog . … The FSM that I am trying to implement is as shown below :-
Verilog Module :-
`timescale 1ns / 1ps
module seq_detector(
input x,clk,reset,
output reg z
);
parameter S0 = 0 , S1 = 1 , S2 = 2 , S3 = 3 …
- 2,331
1
vote
1
answer
262
views
Error while implemeting D_FF from JK_FF in Verilog
The circuit I'm implementing is , as shown in the figure :-
Verilog Module Code :-
`timescale 1ns / 1ps
/* Conversion of a JK Flip Flop to a D Flip Flop
Connections are "J = D" and "K = ~D" …
- 9,763
5
votes
2
answers
44k
views
'1011' Overlapping (Mealy) Sequence Detector in Verilog
I'm designing a "1011" overlapping sequence detector,using Mealy Model in Verilog. … The FSM that I'm trying to implement is as shown below :-
Verilog Module :-
`timescale 1ns / 1ps
module seq_detector(
input x,clk,reset,
output reg z
);
parameter S0 = 0 , S1 = 1 , S2 = 2 , S3 = 3 ; …
- 920
1
vote
Accepted
Debounce circuit design in Verilog
Verilog Module :-
`timescale 1ns / 1ps
module debounce_ckt(
input button,
input clk,
input reset,
output result
);
/*********** Internal Variables **********/
wire Q1,Q2,SCLR,Q3 …
2
votes
5
answers
10k
views
Debounce circuit design in Verilog
The module that I'm trying to implement is as shown below :-
I've written the following Verilog Module :-
`timescale 1ns / 1ps
module debounce_ckt(
input button,
input clk,
output reg result
); …
1
vote
3
answers
5k
views
Error: HDL-Complier-661 Non-net port cannot be mode of input
I'm trying to develop a Verilog code for right shifting as a part of Floating Point ALU. I'm getting the following error in line 7:
Error: HDL-Complier-661 .... …
- 8,935
0
votes
Error: HDL-Complier-661 Non-net port cannot be mode of input
The corrected code :-
`timescale 1ns / 1ps
//Module: Shifts a given numner to the right by an amount (shift_amt)
module right_shifter(
input [3:0] small_mant,
input [2:0] shift_amt,
out …