Search Results
| Search type | Search syntax |
|---|---|
| Tags | [tag] |
| Exact | "words here" |
| Author |
user:1234 user:me (yours) |
| Score |
score:3 (3+) score:0 (none) |
| Answers |
answers:3 (3+) answers:0 (none) isaccepted:yes hasaccepted:no inquestion:1234 |
| Views | views:250 |
| Code | code:"if (foo != bar)" |
| Sections |
title:apples body:"apples oranges" |
| URL | url:"*.example.com" |
| Saves | in:saves |
| Status |
closed:yes duplicate:no migrated:no wiki:no |
| Types |
is:question is:answer |
| Exclude |
-[tag] -apples |
| For more details on advanced search visit our help page | |
Results tagged with synthesis
Search options answers only
not deleted
user 38503
Use this tag when you have questions regarding synthesizable code and the behaviour of the synthesis tool. Synthesis can be either for FPGA or ASIC.
0
votes
Accepted
2
votes
Accepted
How to concatenate unsized parameters
You can SHIFT and OR them
params <= (VT_PARAM1 << 8) | VT_PARAM2; //Assign default 32-bits
- 8,935
4
votes
Accepted
Expressions in Verilog module instantiations
This is legal for input port connections, but output ports can only be connected to nets and/or variables, or a concatenation of those. See section 23.3.3.3 Port connection rules for nets with built-i …
- 8,935
1
vote
How are non-depending variables synthesized with blocking statement?
You should avoid using non-blocking assignments in combinational logic for a number of reasons.
You are correct for variables with no dependencies, it makes no difference for that synthesized logic in …
- 8,935
0
votes
Accepted
Signed wire: synthesize view
And without use in an expression, the declaration disappears in synthesis. …
- 8,935
4
votes
Parametric bit-width assignment in Verilog
There is no need to do this unless you have linting tools and need to suppress warnings about mismatched sizes. Verilog implicitly pads or truncates expressions to the appropriate width.
if(CLEAR)
…
- 8,935
1
vote
synthesis difference between the two almost identical procedural assignment
The job of a synthesis tool is to convert that HDL into a set of Boolean equations and state assignments. It will reduce those equations to an optimal form and the end result should be the same. … BTW, synthesis tools do not interpret X values on signals, they are only used in literals for don't care expressions. In simulation, if s is X, both examples produce a 0 on out. …
- 8,935
3
votes
Accepted
synthesizability of the code
There is a difference between what is allowed by RTL synthesis tools and Behavioral synthesis tools. … Most people are only familiar with RTL, and behavioral synthesis tools have not had much commercial success. …
- 8,935
4
votes
Accepted
Verilog if else if construct
Once you have a completely legal always block, a synthesis tool looks at the flow of variable references across all possible branches. … It's a bit more complicated than that; do read your synthesis tool manual. …
- 8,935
1
vote
SystemVerilog synthesis in Vivado
The issue here is the way Vivado organizes compilation units between files and files of different languages. Verilog did not have this concept except that each compile command lumped all files into on …
- 8,935
1
vote
Accepted
SystemVerilog array of parameters/constants
It's valid syntax for SystemVerilog, but not synthesizable. I'm assuming k gets a value from some code you have not shown. Then you cannot assign it inside the always block as shown.
And you probably …
- 8,935
0
votes
Initial register value in synthesized design is always 0
For Synthesis (and simulation), you need to use a separate initial block.
initial begin
State = non_zero_state;
... …
- 8,935
4
votes
Accepted
Assigning the different value to parameters in Generate block in Verilog
Most simulation and synthesis tools already support this. …
- 8,935
4
votes
Will FPGA synthesis tools ignore unused modules?
I believe there are a number of other mechanisms used to figure out which modules to include in the simulation or synthesis environment. …
- 8,935
1
vote
Difference in synthesis between bitwise AND (&) and logical AND (&&)
All synthesis tools should produce the exact same results. …
- 8,935