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Results tagged with cmos
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user 90588
"Complementary Metal-Oxide Semiconductor" is a process which implements a combination of PMOS and NMOS transistors. Most current digital logic is implemented in CMOS. Its cost-effectiveness due to being so widespread means many other applications have become common as well, such as in analog design, image sensors, telecommunication, etc.
1
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Dynamic power dissipation of a Cmos inverter with relation to it's geometry
In modern circuits the dominant power is C.V².f. Large ICs also have a lot of leakage current at elevated temperatures (sometimes exceeding the capacitive power. Sgoot theough power is usually negligi …
- 20.4k
0
votes
Why does input threshold occur at the unique voltage at which both inverter MOSFETs are in s...
For a CMOS inverter with VDD > sum of VTH's, the range of valid output voltages where both devices are in saturation is from (VIN-VTH_nmos) to (VDD-VIN-|VTH_pmos|). …
- 20.4k
3
votes
Clock feedthrough in 5T OTAs?
When VREF drives the gain node (M2), you get feedthrough from the output to the G of M2 as the output toggles.
If you exchange inputs, then VREF only drives a diode-connected M3, and the swing there i …
- 20.4k
1
vote
Cascode current mirror transistor biasing
If all the FETs are equal sizes, they will have equal VGS.
in your 2nd circuit, V(x) is VGS of M1 with current IREF. Since M0 runs the same current, it will have the same VGS, so V(N) = 2*V(x).
Since …
- 20.4k
1
vote
Accepted
Wider width or more fingers for CMOS transistor to reduce conduction loss in syncrhonous buc...
For your simulation, the only thing that really matters is width*PNOF.
Your 1st curve (90 μm; cyan) at 135 PNOF (total = 90*135 = 12150) has off = 86.7 %. Your last curve (150 um; purple) has the same …
- 20.4k
13
votes
Preference of BJT to MOSFET
CMOS transistors on an integrated circuit can be much much smaller (1000's of times) than BJTs. … BJTs have more precision and specialized uses in some analog circuits, but modern CMOS processes can approach their performance. …
- 20.4k
8
votes
Determining how much load capacitance a 40-series logic IC can safely drive
Therefore you power is ½.C.V^2.f
CMOS ICs are no intended to operate at maximum power dissipation continuously, and there can't be a real guarantee of long term (years) reliability under this condition …
- 20.4k
4
votes
Accepted
CMOS differential pair - common-mode rejection ratio
Remember the ISS current is constant. With different gm's, the transistors may run different DC currents (which sum to ISS). Since you assume ISS is constant, and there are no body effects or ROUT eff …
- 20.4k
2
votes
How to measure the retention time of a capacitor?
Build it and simulate. The capacitor model should include leakage, but if it does not, you will have to find the technology description, oxide thicknesses and lookup the general leakage characteristic …
- 20.4k
0
votes
Push-pull output stage doesn't reach input voltage
S1 is not configured as it should be. You probably want to drive the gates of the FETs to 0 and to 3.3 V. When S1 is open, the gate V on the FETs is not defined (not controlled) -- you need a resistor …
- 20.4k
0
votes
Could we use holes in an NMOS?
In an NMOS, the source and drain are N diffusions. When a channel (electrons) is formed, you can imagine a continuous conductive sheet is formed between S and D at the top surface of the channel.
If y …
- 20.4k
1
vote
Setting multi-fingers in MOSFET in series configuration in Cadence Virtuoso schematic
This is not possible. In a FET with multiple fingers, these are all equivalent to parallel devices.
- 20.4k
3
votes
Why is this circuit a two-stage amplifier?
It is not called a two-stage amplifier in any common usage.
It is a single stage differential amplifier because there is a single node where voltage gain occurs -- at the drain of MN1. The signal ther …
- 20.4k
2
votes
Accepted
Op Amp design - open loop gain 73dB, closed loop gain -200dB
Your open loop gain has a phase of -180 deg. Your VIN+ and VIN- labels are reversed.
This is not a good way to measure AC open loop gain; in general you can't get a good bias point, although it seems …
- 20.4k
2
votes
Variation in Tphl of MOS nand gate due to input patterns
There is no guarantee in a digital library that the A and B FETs are the same size; they can be optimized for different performance.
When you have a A=1; B 0->1 transition, the output may initially go …
- 20.4k