Do more logic gates in series mean more slowing of the output result?

Question

I heard that every logic gate has a propagation delay in nano scale.

As the digital signal propagates through the logic gates, the signal output result will have a delay.

Even though the delay is so short since the unit in nano scale or nano seconds, still we can't underestimate it because the output signal may go to another pin input (serially) which it will give another delay (delay increased) to endpoint output.

Can we conclude that less logic gates means the progress/calculation/propagation will be faster?

We know that the AND operator gives output HIGH only if both inputs are HIGH, else LOW. That speed is standard when it is applied using TTL gates.

What if we apply De Morgan's laws, we know that an A AND B operation is same as NOT(NOT(A) OR NOT(B)). Which is just making more propagation delay if we apply to logic gates even though both operations the give same result output.

We know that massive numbers of logic gates are used in computer nowadays, and we know that every IC (especially CPUs) is made of logic gates. If the CPU has fewer logic gates, will the CPU performance increase?

A science question that I want ask beside engineer question: What factors cause propagation delay happen in a wire?

I can think of: type of wire, transistor technology, temperature. Are there any other factors?

Answer 1

It's definitely the case that frequency can increase with simpler logic. A 3 GHz processor has 333 picoseconds to complete every operation. A few extra picoseconds of delay means lower operating frequency. Nowadays a lot of the delay is wire delay, but logic gate delay still matters.

Performance doesn't necessarily increase though. The gates are there for a reason. They do useful things.

Logic synthesis tools will automatically do things like apply de Morgan's law, and other more complicated transformations, to get the optimal logic implementation based on the available standard cells.

Answer 2

The basic idea is correct. Less gates mean less propagation delay from the input to the output of the network. Given that 99% of the logic these day is synchronous this propagation delay is the upper limit for the clock signal.

In fact one of the major techniques for speeding up logic design is pipelining: if you cut a logic network in the middle so that it does the work in two clock cycles, the propagation of each half is more or less the half so you can rise the clock to squeeze out some nanosecond; buffering and fanout are another big issue since the signal is getting slow and it actually takes a measurable time to travel the 'wires'

At silicon level anyway you don't use 'conventional gates' but some process-specific primitives: some are the usual gates, other are… stranger (in FPGAs the basic primitive is the lookup table, for example). Luckily these days the software does the most of the work (given sufficient time to run)