When and why is it important to route with polygons vs. traces?

Question

I'm (still) a relative beginner in PCB layout. I'm trying to understand in what scenarios it's important to route with polygon areas instead of traces, and in those scenarios, just how important it really is - and why. X/Y disclaimer: the motivation for my question is that the tool I currently use, EAGLE, isn't great at polygons - it's quite a pain: it takes more time, is much more fragile, and I want to learn if and when I can or even should be lazy and use traces.

Consider the following simple layout problem: an LDO (LDL1117) in a SOT-223-4 package with input and output capacitors:

Let's assume a 4-layer board with GND and 3.3 V planes to which we can drop with vias. I would route this as follows (please feel free to critique - I am open to learning):

(Later I'd also pour GND on the top layer, which would "wash out" the GND trace from U1.1 to C2.)

But when I look at "professional" designs, I more often see something like this (again, critique welcome):

I can think of the following pros/cons:

• Higher current-carrying capacity with the polygon areas with less temperature rise.
• For higher frequency signals, lower loop area since the current has more area available to seek the lowest-impedance path.
• Solderability - I think the polygon areas will increase heat sinking and make it harder to hand-solder (more heat required). I'm not sure if there is any impact with professional reflow / wave soldering processes.

Let's look at a more complex example, this time using the ultra-low-noise, ultra-high-PSRR LT3024 LDO. The evaluation board has the following layout¹:

I can reproduce this in EAGLE, but it's such a pain that I find myself wishing I could just do this² instead (this is my mockup, and my reference designators match those of the evaluation board):

So just how much am I sacrificing if I choose to be lazy and use traces instead of polygons? If I have a relatively low-frequency, low-current (< 200 mA in the LT3024 example) circuit, does it really matter? Why, or why not?

_{¹ I've studied the datasheet and evaluation board extensively, and I'm aware of the "special techniques" recommended, such as Kelvin-connecting the output capacitor and stacking the input + and - traces to cancel EMI when post-regulating DC/DCs.}

_{² I noticed I have "U1" silkscreened on a pad. I would fix this in a real design, but I don't think it's necessary to take the time to update the image. Sorry if this bothers you! ;)}

Answer 1

Lots of application-specific reasons but in your example, the big driver is thermal considerations. From the datasheet:

For surface mount devices, heat sinking is accomplished by using the heat spreading capabilities of the PCB and its copper traces. Copper board stiffeners and plated through- holes can also be used to spread the heat generated by the regulator.

And:

The undersides of the DFN and MSOP packages have exposed metal from the lead frame to the die attachment. Both packages allow heat to directly transfer from the die junction to the PCB metal to limit maximum operating junction temperature.

That's why you have a big polygon with a lot of vias in it under the package. For the input and output pins, the datasheet doesn't have any special notes on it, though some do. 200mA is small enough that you wouldn't have to do anything special with trace width in terms of current carrying, but connections to filtering or decoupling capacitors should be low-impedance. Increasing trace width lowers the impedance, which is also why I suspect SET has a polygon on it. Of course, polygons generally have variable effective width as you traverse them so the resulting variations in impedance may not be desirable.

In general, I would start by looking very closely at the datasheet for whichever part is in question. Your LT3042 has a note to look at the DC2246B's datasheet for layout details, which is where you can see the split capacitor layout for C2. Then, I would see if any of the big manufacturers have white papers or app notes regarding layout of the type of component. For example, there's lots of generally-applicable information about switching regulators which are arguably much more picky about which polygons go where.