Is metastability not a concern in CDC if the signal in source clock is at least 3x wide as that of destination clock's period?

Question

There are so much hype and concern over metastability in cross clock domain. If the goal as an ASIC/FPGA designer is to ensure that the signal in source clock get propagated to destination clock even with metastability, consider the case below.

Suppose the input pulse or window signal into the synchronizer is stretched long enough to get latched by the destination clock of the synchronizer FFs twice or more, this ensures that setup & hold are met when the same signal which has been asserted get latched by the same FF 2nd time around; thus the circuit may experience metastability on leading edge of the input signal but the signal will make it out of FF of destination clk. The question is if I can ensure that this happens, do I even need synchronizer FFs (double FFs)? Wouldn't a single FF be sufficient? I guess it depends on what one needs to do with the signal after FF. If I create pulse based on trailing edge signal out of a destination clocked FF, that would work and I would not need to be concerned over whether the circuit experienced metastable condition or not.

Answer 1

How can you guarantee that the hold time requirement of the receiving flip-flop will be met at the end of your wide pulse?

You still need at least two synchronizing flip-flops, I think.

Answer 2

The issue is that the length of time for a metastable flop to resolve could be longer than even your proposed 3x interval. Sure, a metastability event at 3x the clock period will be statistically rarer than if the clock were 1x or 2x, but it will never be zero.

Intel has a useful introductory paper on metastability, here: https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/wp/wp-01082-quartus-ii-metastability.pdf

Answer 3

Looking at this from a qualitative standpoint...

The thing with metastability and its effects is that it is fairly linear with respect to source and destination clock frequencies, but highly non-linear with respect to the setup and hold times and the resolve time of the destination flip flop (highly process/speed dependent).

Say you have a semiconductor process that resolves a metastability condition in 100 ps, and has a setup and hold time of 1 ns. If the source and destinations clocks are 100 Hz and asynchronous wrt one another, the likelyhood of being affected by a metastability event is, very small (though not zero).

On the other hand, if the source and destination clocks are 100 MHz, then the likelyhood of a metastable event occurring at the receiving FF is very much greater, as the equations in the Intel paper hacktastical referenced indicate.

Answer 4

(I'll stick with DFFs and use FPGAs as the example...)

When a DFF in clock domain B (cdB) is driven by a DFF in clock domain A (cdA), the cdB DFF can go metastable if its setup/hold times are not met i.e. the input changes when the cdB clock is changing. You know that already.

Internally, the circuit of each DFF has a very high gain and uses positive feedback. It doesn't stay perfectly balanced in the metastable state - it quickly heads towards one of the rails, into a stable 0 or 1.

Let's now consider cdB DFF_B1 driving a combinatorial circuit that goes into further DFFs. While cdB DFF_B1 output isn't outputting a true 0/1 voltage, the driven combinatorial circuits can also produce invalid or incorrect outputs. When cdB DFF_B1 recovers sufficiently, that combinatorial circuit can correct itself but that circuit's output DFFs may be clocked before it does. The likelihood of that depends on the exact circuit, parts used and the clock frequency.

There are two functions of the second DFF (DFF_B2) in a 2-stage domain input shift register:

(1) When DFF_B1 is clocked and goes from stable into metastable, DFF_B2 will have a whole clock period before it latches in the was-metastable value. In that time, the DFF_B1 output will have headed towards a supply rail and partly/entirely resolved itself. DFF_B2 has a better input voltage to sample and itself resolve.

(2) The DFF_B1 metastable voltage reaches only one further input: DFF_B2's. It doesn't drive any combinatorial logic that can cause the problem detailed above.

So the cdB DFF_B2 is necessary unless the final circuit is simple/slow-clocked enough. I have seen a circuit pass aerospace inspection with only one domain input DFF because it had simple gating and ran at 1 MHz. (It was only found once in the field, otherwise it would have been given two DFFs.)

It's also one of the factors I use when selecting the lowest clock frequency I can be sure of for a digital circuit.

For FPGAs, the DFF recovery time is usually specified in part reliability specifications (haven't checked all manfs but Xilinx/Altera do).

Last time I checked recent families, it was sub-1 ns. This is much shorter than a clock period at the part's maximum clock frequencies (see datasheets).