is it in general possible to implement a frequency doubler completely on FPGA? I saw some implementations on google by delaying the input and XORing it with the original. But they also say that this method is not reliable, and we may not achieve a 50% duty cycle output. I do not want to compromise on duty cycle because i may need to use the doubler 3 times to achieve a x8 frequency
The input clock undergoes a +/- 5% jump in frequency (from 13.56 Mhz) every 30 us.
I tried using a DCM - while the input to the DCM jumps at an instant, the output from the DCM gradually drifts to the required frequency over a span of 20 us. This timing is unacceptable because we jump in frequency every 30 us and we cannot have drifting clock for 20 us of 30 us.
The input clock comes from an external DSP processor, using two DDS (Direct Digital Synthesis) blocks to generate the 13.56 Mhz signal on two ports. The DDS jumps the frequency of the 13.56Mhz every 30 us and also varies its phase from -45deg to +45deg, whilst the other varies phase in the opposite direction. These two 13.56 Mhz signals are enter the FPGA domain.
The FPGA produces 8x signals from these two inputs, totally 16 in number and varying in steps of 45 degrees wrt each other. Currently the FPGA uses a DCM and flip flops to do this. The 13.56 Mhz is fed to the DCM and 8x clock comes out of it. Both the input to the DCM and the output from the DCM are fed to a phase shifter module which shifts the input clock by the period of the 8x clock (45 degrees). All this works fine without frequency jumping but fails due to frequency jumps.