24

It's not so much that NAND is not reliable (although it is less reliable), it's the fact that they are different sorts of memory in how they are accessed and the differences in speed of read/write; they are therefore useful for different applications. NOR's main advantage is that it is random access, which makes it possible to use it to run code. It has a ...


7

NAND flash does not store data error free. It has a (comparatively) high bit error rate. For this reason, pages of data in NAND are stored with redundant data that allows for error checking and correction. This means that when you read a byte from NAND flash, it may have an error. In order to check it or correct it, you need to read the whole page of data to ...


5

XIP requires random access -- the CPU needs to read the instruction stream as it executes it. If there is a loop, it needs to re-read the same instructions again (unless they are cached). If there is a branch, it needs to follow it without a delay. NAND flash interfaces are usually designed to allow blockwise access only. If you want to execute code from ...


5

That's what the "chip enable" (CEn) signals are for. These are active-low (that's what the trailing n means, may also be rendered as a bar over the name in diagrams). You wire all the pins of two chips together except the chip enables, and then wire the CE signals to an address decoder of some sort.


4

The problem with secure erase is that the device has a translation layer in it. On a disk, writing to cylinder X sector Y will always overwrite the same area. On an SSD, the device firmware maintains a list of blank blocks and writes to the next one available, maintaining a table mapping logical addresses to actual flash blocks. There is usually a bit more ...


4

According to the source you linked, Samsung announced a type of NAND flash that stores three bits of information per cell, with eight total voltage states. This is commonly referred to as Triple Level Cell (TLC)... [emphasis added] So it stores 3 bits by using 8 voltage levels, just as you'd expect; not 3 levels as your question text claims. As for why ...


3

Undoubtly, for program memory, the memory of choice is NOR Flash. NAND flash has several issues that make it unsuitable for program storage (NAND has to be accessed in blocks and has the bad habit of corrupting some of its data, so a management system is needed to keep track of blocks usage and of bad records. You don't want to put your program on an ...


3

What are the basic differences between MMC and eMMC storage? In short, there is no fundamental difference. Modern MMC is eMMC molded into plasic case. Or eMMC is a naked BGA chip soldered on-board. "e" simply means "embedded". Support for optional modes changes with revision of specifications, 1.0, 2.0, 3.x, 4.x, now at 5.2, with ever increasing transfer ...


3

There are two differences between MMC and eMMC: eMMC is a solderable BGA, where MMC (and SD etc.) are plug-in cards. The optional SPI 1 wire operational mode in is not supported. Actual operation using a standard MMC / SD interface should be identical to MMC provided the device is properly soldered. eMMC is popular in high reliability applications such ...


3

The headline differences appear to be: Micron device is "Open NAND Flash Interface (ONFI) 1.0-compliant" while the Toshiba isn't. Different page sizes: Micron "x8: 2,112 bytes (2,048 + 64 bytes)" vs Toshiba (2048 + 128). The extra bits are for user-defined tagging and error recovery.


3

First: Be careful not mixing up NAND gates (which are logical circuits) and the gate contact of a MOS transistor. These are two completely different things. The idea having NAND gates makes the internal circuit identical is wrong. Flipflops inside a chip are usually not made from gates but simplified to save space. See e.g. an SRAM cell made from CMOS pass ...


3

The eMMC specification specifies a data bus width of 1, 4 and 8 bits, with the 4 and 8 optional. The interface does not support the slower SPI mode available on SD cards. The vast majority of eMMC devices have 8 bit capable interfaces. The power-up default is 1 bit mode, so that the device will be compatible with older controllers. The physical interface ...


3

The design of NOR-cell memory allows bits to be programmed (written to "0") independently, in any order, and without any risk of disturbing other bits. Some NOR-cell based memory arrays use error-corrected chunks of memory which must be written in chunks of a certain size (e.g. 32 bits) rather than a bit or even byte at a time, but that still makes it ...


3

Try: xxd -r -seek -0x20000000 dump.txt dump.bin xxd -r -p expects input in plain hexadecimal format, without addresses or ASCII. xxd -r without -seek assumes that addresses are zero-based, and will seek or zero-pad its output to skip over regions not present in the dump (the first 0x20000000 = 536870912 bytes).


3

If the attacker has physical access to your device, you've basically already lost. A state-level attacker can do whatever they want. A well-off corporation won’t be too far behind. Even a well-equipped hobbyist with basic tools at home can do a lot. If you have a vulnerability in which physical access to the path between your storage device and processor ...


3

The way to save battery when having a SD card in the system is to use a transisor or FET to switch off the DC power supply to the card connector when you are not needing to access the card for data reading or writing. You want to keep the SD card GND intact with the MCU GND. So make sure to have the power switch turn the SD card VDD on and off. Also to ...


2

How can i make USB memory stick from scratch? The only practical way is to use a USB Flash Drive Controller. Have a look at http://www.siliconmotion.com/A3.2_Features_Detail.php?sn=22 This is quite a complex IC. You could attempt to implement it with a separate processor, NAND controller, USB controller, etc. But you would end up with a PCB about 10cm x ...


2

For the uninitiated : Data sheet hunting First place to look is usually near the end where they will have a complete breakdown of order codes by part, unfortunately not the case with samsung so we will trudge on Clue 1: Clue 2 Clue 3 Clue 4 Combining these clues tells us K9F4G08U0D - 4Gb variant, pinout variant 0 K9K8G08U0D - 8Gb variant, pinout ...


2

Compact Flash is a memory card standard which defines the size of the card, the type of connector, the electrical signals on the connector, and the protocol to be used to read and write to the card. Internally the card will have 1 or more memory IC's that store data. These IC's can be constructed using a technology called either NOR or NAND flash. Originally ...


2

It's implemented as a single array of parallel addressed and accessed memory, with conventional address bus A[n:0], data bus D[15:0] and control bus (/OE, /WE, /CE). It is a NOR flash.


2

I've made analog floating gates with 8-bits per cell, and we actually had a few with 16-bits per cell. The weird "hump chart" that you have is how you read out. If you had a clock and differential amplifier, you check to see if you've changed state from 0 to 1 every clock, and that then tells you how many effective "bits" you have because the "lines charge"...


2

The USB Mass Storage Class with Bulk-Only Transport was a necessity of USB 2.0 link layer limitations, stemmed from the half-duplex nature of USB 2.0 transfers and lack of individualized responses within transactions. So the EHCI controller had to wait for response before issuing some other sense request. This resulted in sub-optimal bus utilization and loss ...


2

No, it's all a game of probabilities. You just define a probability (e.g. \$1-10^{-14}\$) that all pages fulfill that criterion, the manufacturer models the stochastic process that leads to errors and makes observations of that process, and you so get to a probability that indeed your criterion is fulfilled. There's different kind of errors. But yes, ...


2

The difference in read speeds between NOR (few nanoseconds) and NAND (microseconds) is due to the difference in architecture of read logic. just consider the read operation of just one bit (the arrangement of bit and word lines in NOR vs. NAND is a different topic). The read of each memory cell is done by applying convenient voltages to its terminals and ...


2

When being used in the application, the controller will never need to charge the flash cells with the battery, and will instead discharge them, perhaps lowering power draw further by acting as a micro power supply. Is this reasonable, or will I not notice any power savings? No, this is not reasonable. Flash memory is not DRAM. Its cells do not need to be ...


2

if I would replace a NOR Flash in a system with a NAND Flash that contains the same data Trouble is that you usually cannot get a NAND and a NOR flash with the same data interface or protocol. In other words, the existing system won't know how to access the new chip properly. And you really don't want to talk to raw flash directly, as e.g. SD cards are ...


2

Usually because the act of writing does not empty the unwritten-to blocks. So if the first program used blocks 1 to 150 and the new version only uses blocks 1 to 132, then the old information will still exist in blocks 133 to 150 possibly causing errors.


1

USB BOT is a safe bet. I have not seen any system that does not supports that until now. I am pretty sure that USAP will replace BOT in the future, but we are not there yet.


1

First, flash memory is a type of EEPROM (electrically erasable programmable read-only memory), so comparing them either/or doesn't make sense. Second, there is no hard definition of "flash". It's more of a marketing term. It has converged to generally mean a type of EEPROM that is optimized for density, typically at the expense of slow write and erase ...


1

From wikipedia: NAND flash also uses floating-gate transistors, but they are connected in a way that resembles a NAND gate: several transistors are connected in series, and the bit line is pulled low only if all the word lines are pulled high (above the transistors' \$V_T\$). These groups are then connected via some additional transistors to a NOR-style ...


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