24
votes
Why are NOR flashes still used when NAND flashes have a bigger size?
It's not so much that NAND is not reliable (although it is less reliable), it's the fact that they are different sorts of memory in how they are accessed and the differences in speed of read/write; ...
- 1,414
20
votes
Does unused flash memory degrade faster?
Don't discount the possibility of the flash (pen) drive using counterfeit parts and claiming a larger capacity than it actually has. They take the higher address pins and wire them back to the ...
- 8,509
17
votes
Does unused flash memory degrade faster?
Does unused flash memory degrade faster?
no. The opposite is the case.
So my question is: Is there something about the nature of flash memory that can explain empty blocks going bad after some time ...
- 99.9k
9
votes
Accepted
Does cooling the NAND chips on an SSD negatively affect its reliability?
The paper Influence of temperature of storage, write and read operations on multiple level cells NAND flash memories from 2018 shows the following graph, which suggests that writing to flash cells at ...
- 9,749
8
votes
Accepted
What are the "redundant bytes" added to every page of this NAND flash?
The redundant bytes are intended for use by file systems to hold metadata ('data about data').
A common metadata is an Error Correction Code (ECC), calculated on the 2048 data bytes. The ECC is used ...
- 23.8k
7
votes
Accepted
Why can't NAND flash memory be a random access memory?
NAND flash does not store data error free. It has a (comparatively) high bit error rate. For this reason, pages of data in NAND are stored with redundant data that allows for error checking and ...
- 29.5k
6
votes
What are the "redundant bytes" added to every page of this NAND flash?
The redundant cell array is not normally usable, as mentioned in the other answer by TonyM it is used for metadata about memory cell usage and for ECC.
Also it can be used to store timestamps to allow ...
- 296
5
votes
eMMC vc MMC storage
What are the basic differences between MMC and eMMC storage?
In short, there is no fundamental difference. Modern MMC is eMMC molded into plasic case. Or eMMC is a naked BGA chip soldered on-board. "...
- 42.4k
4
votes
What type of FLASH (NAND or NOR) is used on microcontoller?
Undoubtly, for program memory, the memory of choice is NOR Flash. NAND flash has several issues that make it unsuitable for program storage (NAND has to be accessed in blocks and has the bad habit of ...
- 3,335
4
votes
Accepted
How does triple level cell FLASH memory achieve 3 bits per cell?
According to the source you linked,
Samsung announced a type of NAND flash that stores three bits of information per cell, with eight total voltage states. This is commonly referred to as Triple ...
- 134k
4
votes
Accepted
Difference between 24 bit and 32 bit addressing mode in QSPI flash
24 bits can address 16 megabytes. When a larger chip is made like 32 megabyte chip it must be addressed via 32 bits address. It might still have the 24-bit command to allow use of new and larger chips ...
- 172k
3
votes
How to secure an EMMC
If the attacker has physical access to your device, you've basically already lost. A state-level attacker can do whatever they want. A well-off corporation won’t be too far behind. Even a well-...
- 6,456
3
votes
Can I lower flash power consumption by pre-flashing all values to high?
The way to save battery when having a SD card in the system is to use a transisor or FET to switch off the DC power supply to the card connector when you are not needing to access the card for data ...
- 57.9k
3
votes
Accepted
Memory dump size does not match size of MTD partition
Try: xxd -r -seek -0x20000000 dump.txt dump.bin
xxd -r -p expects input in plain hexadecimal format, without addresses or ASCII....
3
votes
Why are NOR flashes still used when NAND flashes have a bigger size?
The design of NOR-cell memory allows bits to be programmed (written to "0") independently, in any order, and without any risk of disturbing other bits. Some NOR-cell based memory arrays use error-...
- 47.3k
3
votes
Why is NAND flash slower than NOR when it comes to reading?
The difference in read speeds between NOR (few nanoseconds) and NAND (microseconds) is due to the difference in architecture of read logic. just consider the read operation of just one bit (the ...
- 31
3
votes
Accepted
Why NAND FLASH is slower than flip-flops?
First: Be careful not mixing up NAND gates (which are logical circuits) and the gate contact of a MOS transistor. These are two completely different things.
The idea having NAND gates makes the ...
- 14.4k
3
votes
eMMC vc MMC storage
There are two differences between MMC and eMMC:
eMMC is a solderable BGA, where MMC (and SD etc.) are plug-in cards.
The optional SPI 1 wire operational mode in is not supported.
Actual operation ...
- 22.6k
3
votes
Accepted
NAND Flash vs NAND EEPROM
The headline differences appear to be:
Micron device is "Open NAND Flash Interface (ONFI) 1.0-compliant" while the Toshiba isn't.
Different page sizes: Micron "x8: 2,112 bytes (2,048 + 64 bytes)" vs ...
- 47.1k
3
votes
What are the "redundant bytes" added to every page of this NAND flash?
The only way to erase and reuse a portion of a NAND flash array is to erase all of the pages in a rather large block. If one wanted to treat a "32 megabyte" flash array as holding 65,000 ...
- 47.3k
2
votes
Interfacing NAND flash to a microcontroller
Your K9GAG08UOE seems to have an 8 bit parallel data bus. You'll need to
read the datasheet on the timing requirements of that, then
you'll need to find a microcontroller that can interface on an 8 ...
- 99.9k
2
votes
How does triple level cell FLASH memory achieve 3 bits per cell?
I've made analog floating gates with 8-bits per cell, and we actually had a few with 16-bits per cell. The weird "hump chart" that you have is how you read out. If you had a clock and differential ...
- 3,312
2
votes
Accepted
Which MSC Sub Class is the best for USB 3.0?
The USB Mass Storage Class with Bulk-Only Transport was a necessity of USB 2.0 link layer limitations, stemmed from the half-duplex nature of USB 2.0 transfers and lack of individualized responses ...
- 42.4k
2
votes
How does NAND reading work?
From wikipedia:
NAND flash also uses floating-gate transistors, but they are connected in a way that resembles a NAND gate: several transistors are connected in series, and the bit line is pulled low ...
- 2,853
2
votes
Accepted
NAND technology - ecc error
No, it's all a game of probabilities. You just define a probability (e.g. \$1-10^{-14}\$) that all pages fulfill that criterion, the manufacturer models the stochastic process that leads to errors and ...
- 99.9k
2
votes
Accepted
SST 39VF1602 - NOR or NAND?
It's implemented as a single array of parallel addressed and accessed memory, with conventional address bus A[n:0], data bus D[15:0] and control bus (/OE, /WE, /CE).
It is a NOR flash.
- 23.8k
2
votes
RAM and Flash structure difference
if I would replace a NOR Flash in a system with a NAND Flash that contains the same data
Trouble is that you usually cannot get a NAND and a NOR flash with the same data interface or protocol. In ...
- 10.5k
2
votes
Accepted
RAM and Flash structure difference
Flash: NOR and NAND
Both NOR and NAND flash use a floating gate to store data. The difference between them is a trade-off of density and speed vs. reliability.
Floating Gate Structure:
From here: ...
- 58.2k
2
votes
Why must a block in NAND SSDs be erased before it can be reprogammed?
Usually because the act of writing does not empty the unwritten-to blocks.
So if the first program used blocks 1 to 150 and the new version only uses blocks 1 to 132, then the old information will ...
- 6,599
2
votes
Can't read an entire page at once (NAND flash)
A first step to understanding this reading issue is to study the NAND Flash connections with an oscilloscope. Do this first without the BusPirate connected. With the circuit board in the same state as ...
- 57.9k
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