21

RTL logic is open-collector, which allows the wire-OR connection (in this case, more precisely, wire-NOR.) The characteristic of wire-OR is that gates only drive low, so even if more than one is enabled, there is no clash. The gates share a common pullup resistor. Wire-OR (that is, open-collector or open-drain) is still used. I2C for example is wire-OR. Wire-...


20

Yes, this is exactly the intended purpose. It's called a wired-OR or wired-AND, depending on your logic. (Or, as Tony points out, even a wired-NOR!) However - you should not do this if you just want twice the amount of current sinking capacity. Only if you want the feature of being able to switch using separate inputs. Current will likely not be shared ...


17

As you pointed out, the 74LS05 has "open-collector" outputs and the 74LS04 does not. There are two general types of outputs in digital circuitry: push-pull and open-collector (OC). The latter name dates back to when BJT (bipolar junction transistors) were used in the output stage, for example TTL logic like the LS series; you will also see the nomenclature ...


12

As far as I know, SPI lines are always actively driven in both directions. I sometimes put a pulldown on the MISO line because it could be floating for extended periods of time. Only the slave with slave select asserted is allowed to drive the line, so when no slave is selected, the line floats. Floating MISO doesn't cause any data problems because it ...


12

Usually a Logic Low is a low voltage, normally near Ground/Zero volts, and a Logic High is a higher voltage near the positive supply voltage. There is a range of voltages between Low and High where the input state is undefined - we don't know whether the circuit will consider it as a High or Low. If the input of a logic gate is not connected, that ...


11

...as long as the enable signals for the tri-states are mutually exclusive... The trick is how to do this without adding another wire, or multiple wires to tell each peripheral when it is allowed to drive the bus. The main advantage of I2C is that it only uses two wires, and two pins on each chip connected to the bus. If you're willing to trade pins for ...


10

That open collector output ... when off, it will have some leakage (possibly microamps) depending on temperature. That can supply enough base current to turn Q2 on, at least partially. The simulation might not model that leakage accurately. R1 pulls Q2 base to 5V against that leakage, ensuring Q2 is fully off.


9

The main reason for using open-collector is so that several comparators can have their output connected together in a wired OR gate. All the open collectors can be tied together to a single resistor without any conflicts between comparators. This would not have been easy to do when your comparator has also the capability to source current at its output. ...


9

I am answering my own question because I think it fits better than updating the question. Feel free to comment I update the post accordingly if it does not suit the EE.SE guidelines. As @dim suggested, I have contacted the manufacturer and I have received an answer. The IC inside the Adam-4055 driving Digital Outputs is a ULN2803 (specs, info). The reason ...


7

how is this any more "poor man's logic gate" than all the rest in RTL? Replace your logic gates in your diagram with the actual transistors and resistors, and you'll see that the output of a gate in RTL is "pull-down" logic. Whenever either NOR1 or NOR2 outputs "low", the common node is pulled towards ground. This is a NOR gate, ...


7

is Low and High used as an indication of lower input voltage and higher input voltage ? Yes, but some logic families also have current requirements. With TTL, for instance, a logic 0 is not only a low voltage but the driving stage must be able to sink 1.6 mA of current from the input. And if Zero used as a low input voltage then isn't no input can also be ...


6

I always thought of comparators as the simplest A-D converter. You may want a different supply voltage on the analog side (maybe +/-15V or something) and the output going to a different digital voltage. (+5 V perhaps.) The open collector lets you easily adjust the output voltage reference.


6

sometimes a pullup on MISO seems to be used This is done mostly on SD cards, because they come out of reset as open drain and must be switched into SPI with a command. You would also need a pullup/down when the slave may be disconnected somehow to put the non-driven line to a known state. if totem pole configuration is the standardized driving method for ...


6

That open collector output V o is not pulled up internally according to the datasheet. Zero mention of it, and every diagram shows a simple npn open collector. Power the VCC at 5V, and pull up V o to 3.3V vía a external resistor or your microcontroller internal pull-up resistor. Worst case, use a voltage divider to bring the signal at V o down to 3.3V.


5

Don't connect the solenoid to ground, connect it to Vcc and use the MOSFET with its source tied to ground - drain to the other end of the solenoid. Put the protection diode across the solenoid, cathode to Vcc. Now, if you do this you'll most likely find that it behaves much more as you would expect it to because the MOSFET will turn on properly. You need to ...


5

Open collector outputs are always hi-Z when they are high. The only way to source current from an OC output when they are high is via an external pullup.


5

I would add that it is possible to design a digital device that can detect an open input vs. high input vs. low input, thus having a three-state input. This is done by alternately connecting the input to relatively high-resistance pull-up and pull-down resistors. This does result in fairly low sampling rates as the device must let the input settle after ...


4

By far the lowest component count solution to the problem of simulating the TACH signal from a fan is to use a small microcontroller (MCU) that can measure the PWM input signal duty cycle. The PWM signal can be measured two ways with the MCU either by using a timer to directly measure the high / low pulse widths OR by filtering the PWM via an R/C circuit to ...


4

Yes, 3.3V should work. The datasheet says: So as long as you can drive the \$ \overline{SHDN} \$pin lower than 0.25V when turning it off and higher than 2V when turning it on, it should work as expected.


4

Yes, you certainly can wire the two outputs together. Open drain and open collector just reflect the different technologies used inside the chips. Keep in mind that 'wired or' is assuming input and output signals are inverted, so it's really an AND gate (both outputs must high-Z for the combined output to go high).


4

If U1 is also running from 5 V in your example, then it doesn't matter at all. Either way there will be no current thru the LED when the output is not actively pulling low. It won't matter that it is actively driving high or just open. There are two cases where it might make a difference: Not the same power voltage. Open drain outputs can be made to ...


4

There are two specific features that require open-drain lines. The first is clock-stretching, where a slave can hold the clock (SCL) low to delay the transaction while it processes data. The second is multi-master arbitration, where two or more masters try to transmit at the same time. The arbitration is done by having a master stop transmitting when it sees ...


4

It turns out I wasn't sampling the GPIO long enough. I wrote a little Raspberry PI kernel module to sample the GPIO as fast as possible for 3 seconds, and record a semi-accurate trace. Here's what showed up on the wire after one second: In summary, the N64 waits one second after boot to ask the controllers to identify themselves with 0x00 followed by a stop ...


4

You can use a GPIO as open drain by programming it differently. If you leave it programmed to output mode, then set the output data to 0 or 1, it behaves as a push pull output. If you leave the output data set to 0, then program the mode to input or output, it behaves as an open drain output. Although this is a fairly common pattern, it's worth leaving ...


4

What puzzles me is that it seems inefficient. In order to switch the output off, I need to effectively short the circuit in order to pull it to ground. Is my interpretation correct? If not, why not? Figure 1. The opto-isolator's output is shown with RL, the load. What you are missing is that RL is the load. When the output is pulled low there is voltage ...


4

At first glance, the circuit you show looks a lot like a single channel of a ULN2003A 7-channel Darlington driver. Each ULN2003A channel is a Darlington driver: a circuit where one transistor directly drives another transistor to get a combined current gain far higher than the gain of either transistor. The COM diode in each ULN2003A channel is useful if any ...


4

Maybe, but you need to ensure that the Vol from the open-drain output guaranteed to be sufficiently low to ensure that the transistor is fully off under worst-case conditions with the value of R1 that you need to properly drive the base (typically something like the relay coil current divided by 10 or 20). A guarantee of 300mV is usually sufficient. ...


4

Zero’s and one’s (low & high) are digital defined by analog values with a margin in between for transitions and noise. No output is floating or called tri-state used on bidirectional busses. However CMOS must never be designed with no input for many reasons and must be terminated low or high as required. No input on TTL is hi, but for noise reasons ...


3

Open drain allows there to be multiple masters on the same bus. If two masters try to transmit at the same time with push-pull drivers, they can damage each other, and even if they don't it's hard to tell which master will win. Open drain acts as a "wired AND", which makes it easy to share the line and arbitrate collisions. CAN does something similar, ...


3

There really isn't an issue with that. Open drain and open-collector are essentially the same in this application. Two things to watch out for: Make sure you get your polarities right and that you need an OR gate and not a NOR gate because the open-collector/open-drain style often invert your signal. If the output of either opamp is high, then the output ...


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