All Questions
Tagged with computer-architecture pipeline
14 questions
7
votes
4
answers
1k
views
How does pipelined CPU access both code and data memory in real life?
In the Digital Design and Computer Architecture RISC-V Edition page 442, a pipelined CPU is designed with separate instruction and data memories, as shown in the figure below.
However, this picture ...
- 193
4
votes
1
answer
162
views
Understading CPU pipeline stages
I'm working on implementing a CPU that needs a three-stage pipeline. The division of those stages is open for me to determine.
I am struggling to comprehend how the stages are counted. While some ...
- 75
3
votes
1
answer
116
views
On understanding tradeoffs associated with pipeline depth
In Weste and Harris's CMOS VLSI Design, they write the following in the context of a discussion about how different levels of design abstraction interact but, to be clear, my question is about the ...
- 1,219
0
votes
1
answer
218
views
Understanding decode stage of x86 fetch-decode-execute pipeline and its (lack of) register requirements
FDE pipeline has register requirements for the F & D stages: For fetching an instruction from memory, the instruction pointer register points to the memory location of the next instruction to be ...
0
votes
1
answer
152
views
Why do we need stalls even if branches can be determined?
I am learning about pipelining and was reading about control hazards from the book Computer Organization and Design: The Hardware/Software Interface (MIPS Edition). There is a paragraph in the book (...
- 103
0
votes
1
answer
64
views
Designing instruction emulating swap on a MIPS ISA with only 2 registers
In a typical MIPS ISA, you have only 2 working registers. But you have a large number of ALU units.
How to design an instruction to emulate swap?
- 87
0
votes
1
answer
468
views
How does CPU control implement pipeline stall [closed]
The original question was deemed lack of focus. This post is specifically about cpu pipeline stall.
How does synchronous microarchitecture implement pipeline stall when a cache miss occurs during ...
- 123
-1
votes
3
answers
2k
views
What is the difference between stalling and flushing in a microprocessor?
As the title suggests, I want to understand the difference. Attaching the reference.
- 107
1
vote
0
answers
164
views
How much faster is the ideal machine without the memory structural hazard versus the machine with the hazard?
I am learning computer architecture and organization. I have the following doubt. Given below is a question along with its solution but I think that the solution is wrong. You can see the question ...
- 375
3
votes
1
answer
483
views
With what stage of the branch instruction does the IF stage executes if the branch is taken?
I am learning computer architecture and organization. I have the following doubt. Given below is a question along with its solution but I think that the solution is wrong.
Consider an instruction ...
- 375
1
vote
0
answers
61
views
Difficulty in understanding the concept of operand forward in pipeling and when to use split phase
Given below is a question from \$\text{GATE } 2015 \text{ CS}\$ paper,
Consider the sequence of machine instruction given below:
\begin{array}{ll} \text{MUL} & \text{R5, R0, R1} \\ \text{DIV} &...
- 155
1
vote
1
answer
119
views
Throughput increase/decrease by how much percent
I am learning computer architecture and organization. I am stuck in the following question. Can someone please help me?
The stage delays in a 5-stage pipeline are 300, 200, 100, 400 and 350
...
- 375
4
votes
1
answer
802
views
Is it possible to remove the write back stage in 5-stage pipeline?
In this graph, can we simply remove the write back stage since the mux is pushed back into the memory access stage and there is no logic in the write back stage. Is it because of the register file ...
- 113
2
votes
1
answer
164
views
Doubt in pipelining forwarding in MIPS
I am fairly new to computer architecture and having a tough time solving problems based on pipelining. I was trying to solve a problem from this pdf I found on Google
I have a doubt in part ...
- 123