Questions tagged [x86]
x86 is an Intel CPU architecture that originated with the 16-bit 8086 processor in 1978. Today, the term x86 is used generally to refer to any 32-bit processor compatible with the x86 instruction.
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Intel Tiger Lake UP3 motherboard bring up - PLTRST# gets asserted during boot-up
I'm in the middle of doing bring up to my tiger lake processor motherboard, during boot, the system reading from bios SPI flash reaches 0x00214A7D address.
I understood that 0x00214A7D address has to ...
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x86 Motherboard Bring Up - Intel Tiger Lake UP3 CPU
For those who has experience with Intel x86 motherboard design and bring up.
I'm in the middle of motherboard bring-up that has Intel Tiger Lake UP3 CPU.
Seems like I had a good run so far at power-up ...
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maximum memory supported by processor - why often stated less than 1TB?
I want to understand technical details of limitations of maximum memory size a system / processor can support. Below what I was able to find via web search to date Wiki:
Modern 64-bit processors such ...
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Would it be possible to prototype a low-powered 386SX design on a breadboard?
According to the datasheet the low power version of the 386SX comes in a QFP100 and can be run at as low as 2MHz. I'm wondering if it might be possible to prototype a system on a standard solderless ...
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Why exactly does the x86 (primarily x86-64) instruction set consume more power than reduced instruction sets like arm?
While I'm aware this is somewhat a copy of this question, I've not been more than a browser of any part of stack exchange, and so I couldn't ask this in a comment replying to @supercat 's answer. The ...
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Internal differences between CPUs of the same architecture
What is the difference between, for example an Intel i3-4005U (1.7 GHz) and an Intel i3-4025U (1.9 GHz)? These CPUs are from the same generation, have the same amount of cores, cache, iGPU, and ...
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Is a major upgrade to JTAG's bus bandwidth possible without changing much else on a processor / board?
Based on my previous question about JTAG:
Does the JTAG port have enough bandwidth to monitor the state changes of all cores on an x86 machine, or even one at a time?
Answer: No
JTAG is a bit-serial ...
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Does x86 architecture allow a debugger to access the busses and registers without halting the debugged core?
An excerpt form the JTAG website
Many silicon architectures such as PowerPC, MIPS, ARM, x86 built an entire software debug, instruction tracing, and data tracing infrastructure around the basic JTAG ...
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Does the JTAG port have enough bandwidth to monitor the state changes of all cores on an x86 machine, or even one at a time?
Based on my related question on Info Sec SE I want to know if I could track all changes to register state (and perhaps memory too) on multiple cores of an x86-64 CPU.
Some of my research so far ...
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How to choose between PCIE and USB3 in a CPU pin?
While looking at Validation Reference Platform for 11th Gen Intel CPU (Tiger Lake UP3), I noticed that some pins for the MCP (Multi Chip Package, which is a package that includes PCH+CPU on the same ...
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What does the 8086 CPU do with the data returned from an address in RAM?
I understand how a CPU works fairly well, but there is this one thing which I've never really gotten the hang of.
Say we have an Intel 8086 CPU (16 bits wide registers) which is about to fetch its ...
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Why are ALE and INTA not floated during Hold on an 8088 while other outputs are?
When the 8088 goes into hold, every output is tri-stated apart from HLDA (obviously), ALE and INTA. Given that the purpose of hold is to allow an external device to control the bus, like a DMA ...
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IO port register whose address is software defined (x86)
I want to do something that I assume must be fairly common in digital logic/bus design. It’s for a new expansion card for an old 8088-based computer. This isn’t some kind of college homework project.
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Reason for x86 reset vector being at 0xFFFFFFF0 instead of 0xFFFFFFFF
The top answer to this question on Super User gave an explanation that was satisfactory to me at first as to why the reset vector is not at address 0 (afterwards , I realized that it doesn't why the ...
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Accessing odd address memory locations in 8086
I am a beginner in microprocessors. Apologies if my question is too naive.
The memory section of the 8086 processor is divided into two segments: even and odd to allow the CPU to fetch 16 bits in one ...
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Can a micro operation pass multiple pipeline stages with a single clock cycle?
I'm learning a CPU architecture and currently found some high-level description of Intel x86_64 CPUs architecture. By the high level description I mean something like the following micro-op flow (...
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Memory interfacing with 8086: IP/CS pointers in EPROM while RAM addresses start at F0000H
Design an interface between 8086 CPU and two chips of 16K x 8 EPROM and
two chips of 32K x 8 RAM. Select the starting address of EPROM suitably.
The RAM address must start at F0000H.
I have a ...
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Buses and the ALU in the 8086
Intel's 8086 manual shows the following diagram for the CPU's architecture (in page 2-5):
If I understand correctly, the ALU's two operands and result are retrieved from / sent to the same 16-bit bus....
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8086 doesn't write to external memory [duplicate]
we are working on a circuit containing a 8086 and 8x(2KB) external memories (6116). the problem is that all control signals are asserted correctly, the address and data is provided but they are not ...
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why ARM architecture necessarily dominates the IOT market? [closed]
I would like to understand why do we use ARM for routers, cell phones, cameras, refrigerators, smart tv, and everything. instead of using any other architecture like x86.
What are the advantages of ...
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Relationships between instruction execution and clock cycle in modern CPUs
I have some misunderstanding about what clock cycle really is. I generally understand a schema how CPU processes an instruction. Intel manual describes the schema for Intel NetBurst architecture as
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Where the appropriate word size is selected for the operand?
This question is about a 32 bit Intel Chip using x86 assembly. My question specifically is what happens when you do the mov reg, mem instruction where the memory operand is a word (16 bits) from DRAM. ...
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What is the difference between a BIOS chip and a PCH
From what I can gather, the BIOS chip is a loadable memory space that handles initial I/O, system checks and CAN configure certain things like power states and clock rates, before handing operation ...
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is the intel quark capable of running an opencv webcam unity application for linux? [closed]
I built a fairly simple application in Unity that uses a webcam and opencv to overlay graphics in realtime to a user's face. I am looking for a low cost microcontroller/computer to run the ...
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Fan-out of the Intel 8086
I'm studying Intel 8086 processor.
I can't understand why the "Fan-out" column is like that in the table below
I understand that only one "74 family" chips or five "74LS family" gates can be ...
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ARM chips that lack boot ROMs [closed]
This isn't anywhere near as true as it used to be, but I consider one difference between x86 platforms and ARM platforms to be whether or not booting involves the use of a mask ROM at reset to ...
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Anyone knows how X86 platform set the PCIe bifurcation at boot up?
I got a question about the PCIe bifurcation setting when booting up in X86 system.
Normally, we can set the PCIe controller to be X16, two X8, or four X4 in the UEFI shell menu. However, there is an ...
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How does the Intel 8086/88 know when to assert the IO/M signal?
Consider an Intel 8088 processor with a standard, parallel RAM and ROM implementation that also supports address/data bus access to various external peripherals like analog-to-digital converters (ADCs)...
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Intel 8259A: why use A0 when there's nothing to address?
I am in the process of writing a driver for the Intel 8259A PIC and using the corresponding datasheet for reference.
The datasheet contains a picture of the controller and its connection to the ...
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Intel 8042: what are "test inputs"?
I've implemented a driver for the Intel 8042 (keyboard controller in the IBM PC AT). The IBM 5170 (PC AT) Technical Reference served as my, well, reference for that.
The output port and the test ...
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Intel 8259A: mysterious T bit doesn't fit the pattern
I'm implementing a driver for the Intel 8259A PIC for x86. To do this properly, I am reading the Intel 8259A PIC Datasheet. It is halfway comprehensible even for someone who approaches controller ...
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How is register access done in case of X86 architecture when there is only In and OUT command for ports?
In ARM architecture the registers of a peripheral are mapped to the RAM so we can access the register using the RAM.
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Why do I need a page directory?
I've found that image:
and cannot find a reason why there is page directory ? I think that it could save time, if the process (or processes), especially the CR3 ...
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Does A20 line only disable 20th it or all bits from 20th and above?
According to this picture:
Only the 20th bit is disabled until we enable it with keyboard controller (or BIOS). Based on the diagram, I think that the wrap around feature is retained for old programs ...
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8259A End of Interrupt (EOI) signal question
In the x86 architecture, when a hardware interrupt's ISR finishes you need to tell the 8259A chip that it is done and you send an EOI signal to the chip. After that you can return from the ISR using ...
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Capturing x86 register value changes in hardware i.e. at circuit level
I need to find a way of observing (on another 'monitor' machine) changes to registers critical to the address translation process on x86 platforms - including IDTR, GDTR, CR3, etc. This monitoring ...
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TECs and Desktops
Recently I was doing a little research about SFP/SFP+ modules by reading the SFF-8472 spec.
In there, I learned that SFP modules use TECs (Thermoelectric Coolers) to "pump" heat away from the load.
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General purpose cpu as logic analyser better / worse than dedicated FPGA implementation
This question relates to building a cheap but capable logic analyzer. I had the idea of using an x86 cpu that was running a program that could fit in the fastest cache that would just read data from a ...
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Effective Address calculation time on 8086/8088
I've started designing an implementation of an 8088 from scratch with the goal of being cycle-exact. I can understand the reasoning behind the number of clock cycles for most instructions, however I ...
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Reverse-engineering VGA
I got a x86-based firewall, produced by Stonesoft. It has serial interface, but it would be easier to install new operating system if I would get VGA output from the device. I discovered promising ...
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What is Pipeline Flushing in microprocessors
I am reading the book "Writing Operating System from Scratch" by Nick Blundell. In one of the chapters, it is explained how we make transition from 16bit mode to 32bit mode. It says that before moving ...
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memory segmentation in 8086
If the external memory (1 MB) in 8086 based system is segmented into code, data, stack and extra which are all 64 kB, what do we do with the rest of the memory? Does it go waste?
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Why ARM cores consumes relatively lower power than x86 [closed]
Why ARM cores consume little power compared with x86 CISC implementations?
What are the valid reasons?
because of it's fabrication technology?
Could this be right? ARM cores have been fabricated ...
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The modification of Instruction set [closed]
Recently I came to know that x86 instruction set can be regarded as obsolete. It should have been out of order a decade ago. Instead of being helpful, it can be called as burden. The only advantage of ...
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Can a disconnected pin on DDR3 SDRAM go undetected?
I was testing some DDR3 SODIMM modules using Memtest86+ on a Lenovo Thinkpad T520. I re-tested a module that I previously marked faulty and it came out fine.
So I wonder if it's possible that the ...
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