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Questions tagged [x86]

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0
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1answer
36 views

Relationships between instruction execution and clock cycle in modern CPUs

I have some misunderstanding about what clock cycle really is. I generally understand a schema how CPU processes an instruction. Intel manual describes the schema for Intel NetBurst architecture as ...
0
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1answer
41 views

Where the appropriate word size is selected for the operand?

This question is about a 32 bit Intel Chip using x86 assembly. My question specifically is what happens when you do the mov reg, mem instruction where the memory operand is a word (16 bits) from DRAM. ...
0
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0answers
41 views

How does a slave PIC 8259 gets enabled via CS

I was trying to wrap my head around the interfacing between 8086 and 8259 PICs. Specifically, the Chip Selection and I/O port mapping. According to a diagram I saw here, the 8086's address lines A0, ...
0
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1answer
45 views

What is the difference between a BIOS chip and a PCH

From what I can gather, the BIOS chip is a loadable memory space that handles initial I/O, system checks and CAN configure certain things like power states and clock rates, before handing operation ...
0
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2answers
54 views

is the intel quark capable of running an opencv webcam unity application for linux? [closed]

I built a fairly simple application in Unity that uses a webcam and opencv to overlay graphics in realtime to a user's face. I am looking for a low cost microcontroller/computer to run the ...
12
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1answer
2k views

Fan-out of the Intel 8086

I'm studying Intel 8086 processor. I can't understand why the "Fan-out" column is like that in the table below I understand that only one "74 family" chips or five "74LS family" gates can be ...
0
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2answers
116 views

ARM chips that lack boot ROMs [closed]

This isn't anywhere near as true as it used to be, but I consider one difference between x86 platforms and ARM platforms to be whether or not booting involves the use of a mask ROM at reset to ...
0
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1answer
142 views

Anyone knows how X86 platform set the PCIe bifurcation at boot up?

I got a question about the PCIe bifurcation setting when booting up in X86 system. Normally, we can set the PCIe controller to be X16, two X8, or four X4 in the UEFI shell menu. However, there is an ...
2
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1answer
261 views

How does the Intel 8086/88 know when to assert the IO/M signal?

Consider an Intel 8088 processor with a standard, parallel RAM and ROM implementation that also supports address/data bus access to various external peripherals like analog-to-digital converters (ADCs)...
0
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1answer
290 views

Intel 8259A: why use A0 when there's nothing to address?

I am in the process of writing a driver for the Intel 8259A PIC and using the corresponding datasheet for reference. The datasheet contains a picture of the controller and its connection to the ...
5
votes
1answer
215 views

Intel 8042: what are “test inputs”?

I've implemented a driver for the Intel 8042 (keyboard controller in the IBM PC AT). The IBM 5170 (PC AT) Technical Reference served as my, well, reference for that. The output port and the test ...
2
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1answer
72 views

Intel 8259A: mysterious T bit doesn't fit the pattern

I'm implementing a driver for the Intel 8259A PIC for x86. To do this properly, I am reading the Intel 8259A PIC Datasheet. It is halfway comprehensible even for someone who approaches controller ...
1
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2answers
191 views

How is register access done in case of X86 architecture when there is only In and OUT command for ports?

In ARM architecture the registers of a peripheral are mapped to the RAM so we can access the register using the RAM.
2
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2answers
1k views

Why do I need a page directory?

I've found that image: and cannot find a reason why there is page directory ? I think that it could save time, if the process (or processes), especially the CR3 ...
0
votes
1answer
55 views

Does A20 line only disable 20th it or all bits from 20th and above?

According to this picture: Only the 20th bit is disabled until we enable it with keyboard controller (or BIOS). Based on the diagram, I think that the wrap around feature is retained for old programs ...
0
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1answer
1k views

8259A End of Interrupt (EOI) signal question

In the x86 architecture, when a hardware interrupt's ISR finishes you need to tell the 8259A chip that it is done and you send an EOI signal to the chip. After that you can return from the ISR using ...
0
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1answer
92 views

Capturing x86 register value changes in hardware i.e. at circuit level

I need to find a way of observing (on another 'monitor' machine) changes to registers critical to the address translation process on x86 platforms - including IDTR, GDTR, CR3, etc. This monitoring ...
1
vote
2answers
93 views

TECs and Desktops

Recently I was doing a little research about SFP/SFP+ modules by reading the SFF-8472 spec. In there, I learned that SFP modules use TECs (Thermoelectric Coolers) to "pump" heat away from the load. ...
1
vote
1answer
120 views

General purpose cpu as logic analyser better / worse than dedicated FPGA implementation

This question relates to building a cheap but capable logic analyzer. I had the idea of using an x86 cpu that was running a program that could fit in the fastest cache that would just read data from a ...
5
votes
2answers
544 views

Effective Address calculation time on 8086/8088

I've started designing an implementation of an 8088 from scratch with the goal of being cycle-exact. I can understand the reasoning behind the number of clock cycles for most instructions, however I ...
3
votes
1answer
743 views

Reverse-engineering VGA

I got a x86-based firewall, produced by Stonesoft. It has serial interface, but it would be easier to install new operating system if I would get VGA output from the device. I discovered promising ...
2
votes
2answers
3k views

What is Pipeline Flushing in microprocessors

I am reading the book "Writing Operating System from Scratch" by Nick Blundell. In one of the chapters, it is explained how we make transition from 16bit mode to 32bit mode. It says that before moving ...
3
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3answers
2k views

memory segmentation in 8086

If the external memory (1 MB) in 8086 based system is segmented into code, data, stack and extra which are all 64 kB, what do we do with the rest of the memory? Does it go waste?
1
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1answer
3k views

Why ARM cores consumes relatively lower power than x86 [closed]

Why ARM cores consume little power compared with x86 CISC implementations? What are the valid reasons? because of it's fabrication technology? Could this be right? ARM cores have been fabricated ...
-7
votes
2answers
158 views

The modification of Instruction set [closed]

Recently I came to know that x86 instruction set can be regarded as obsolete. It should have been out of order a decade ago. Instead of being helpful, it can be called as burden. The only advantage of ...
0
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2answers
149 views

Can a disconnected pin on DDR3 SDRAM go undetected?

I was testing some DDR3 SODIMM modules using Memtest86+ on a Lenovo Thinkpad T520. I re-tested a module that I previously marked faulty and it came out fine. So I wonder if it's possible that the ...