Questions tagged [x86]
x86 is an Intel CPU architecture that originated with the 16-bit 8086 processor in 1978. Today, the term x86 is used generally to refer to any 32-bit processor compatible with the x86 instruction.
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Buses and the ALU in the 8086
Intel's 8086 manual shows the following diagram for the CPU's architecture (in page 2-5):
If I understand correctly, the ALU's two operands and result are retrieved from / sent to the same 16-bit bus....
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8086 doesn't write to external memory [duplicate]
we are working on a circuit containing a 8086 and 8x(2KB) external memories (6116). the problem is that all control signals are asserted correctly, the address and data is provided but they are not ...
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Is an IOMMU a part of the PCIe or the other way around?
AFAIK, the PCI is just another bus that can serve as the parent bus for others like USB but is nevertheless capable of just being a standalone bus without any bridges as well. Also the PCIE comes with ...
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1answer
168 views
why ARM architecture necessarily dominates the IOT market? [closed]
I would like to understand why do we use ARM for routers, cell phones, cameras, refrigerators, smart tv, and everything. instead of using any other architecture like x86.
What are the advantages of ...
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1answer
40 views
Relationships between instruction execution and clock cycle in modern CPUs
I have some misunderstanding about what clock cycle really is. I generally understand a schema how CPU processes an instruction. Intel manual describes the schema for Intel NetBurst architecture as
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1answer
44 views
Where the appropriate word size is selected for the operand?
This question is about a 32 bit Intel Chip using x86 assembly. My question specifically is what happens when you do the mov reg, mem instruction where the memory operand is a word (16 bits) from DRAM. ...
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1answer
189 views
What is the difference between a BIOS chip and a PCH
From what I can gather, the BIOS chip is a loadable memory space that handles initial I/O, system checks and CAN configure certain things like power states and clock rates, before handing operation ...
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2answers
77 views
is the intel quark capable of running an opencv webcam unity application for linux? [closed]
I built a fairly simple application in Unity that uses a webcam and opencv to overlay graphics in realtime to a user's face. I am looking for a low cost microcontroller/computer to run the ...
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1answer
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Fan-out of the Intel 8086
I'm studying Intel 8086 processor.
I can't understand why the "Fan-out" column is like that in the table below
I understand that only one "74 family" chips or five "74LS family" gates can be ...
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2answers
152 views
ARM chips that lack boot ROMs [closed]
This isn't anywhere near as true as it used to be, but I consider one difference between x86 platforms and ARM platforms to be whether or not booting involves the use of a mask ROM at reset to ...
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1answer
170 views
Anyone knows how X86 platform set the PCIe bifurcation at boot up?
I got a question about the PCIe bifurcation setting when booting up in X86 system.
Normally, we can set the PCIe controller to be X16, two X8, or four X4 in the UEFI shell menu. However, there is an ...
2
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1answer
323 views
How does the Intel 8086/88 know when to assert the IO/M signal?
Consider an Intel 8088 processor with a standard, parallel RAM and ROM implementation that also supports address/data bus access to various external peripherals like analog-to-digital converters (ADCs)...
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1answer
370 views
Intel 8259A: why use A0 when there's nothing to address?
I am in the process of writing a driver for the Intel 8259A PIC and using the corresponding datasheet for reference.
The datasheet contains a picture of the controller and its connection to the ...
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1answer
246 views
Intel 8042: what are “test inputs”?
I've implemented a driver for the Intel 8042 (keyboard controller in the IBM PC AT). The IBM 5170 (PC AT) Technical Reference served as my, well, reference for that.
The output port and the test ...
2
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1answer
80 views
Intel 8259A: mysterious T bit doesn't fit the pattern
I'm implementing a driver for the Intel 8259A PIC for x86. To do this properly, I am reading the Intel 8259A PIC Datasheet. It is halfway comprehensible even for someone who approaches controller ...
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2answers
211 views
How is register access done in case of X86 architecture when there is only In and OUT command for ports?
In ARM architecture the registers of a peripheral are mapped to the RAM so we can access the register using the RAM.
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2answers
2k views
Why do I need a page directory?
I've found that image:
and cannot find a reason why there is page directory ? I think that it could save time, if the process (or processes), especially the CR3 ...
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1answer
69 views
Does A20 line only disable 20th it or all bits from 20th and above?
According to this picture:
Only the 20th bit is disabled until we enable it with keyboard controller (or BIOS). Based on the diagram, I think that the wrap around feature is retained for old programs ...
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1answer
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8259A End of Interrupt (EOI) signal question
In the x86 architecture, when a hardware interrupt's ISR finishes you need to tell the 8259A chip that it is done and you send an EOI signal to the chip. After that you can return from the ISR using ...
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1answer
96 views
Capturing x86 register value changes in hardware i.e. at circuit level
I need to find a way of observing (on another 'monitor' machine) changes to registers critical to the address translation process on x86 platforms - including IDTR, GDTR, CR3, etc. This monitoring ...
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2answers
95 views
TECs and Desktops
Recently I was doing a little research about SFP/SFP+ modules by reading the SFF-8472 spec.
In there, I learned that SFP modules use TECs (Thermoelectric Coolers) to "pump" heat away from the load.
...
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1answer
127 views
General purpose cpu as logic analyser better / worse than dedicated FPGA implementation
This question relates to building a cheap but capable logic analyzer. I had the idea of using an x86 cpu that was running a program that could fit in the fastest cache that would just read data from a ...
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2answers
562 views
Effective Address calculation time on 8086/8088
I've started designing an implementation of an 8088 from scratch with the goal of being cycle-exact. I can understand the reasoning behind the number of clock cycles for most instructions, however I ...
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1answer
793 views
Reverse-engineering VGA
I got a x86-based firewall, produced by Stonesoft. It has serial interface, but it would be easier to install new operating system if I would get VGA output from the device. I discovered promising ...
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2answers
3k views
What is Pipeline Flushing in microprocessors
I am reading the book "Writing Operating System from Scratch" by Nick Blundell. In one of the chapters, it is explained how we make transition from 16bit mode to 32bit mode. It says that before moving ...
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3answers
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memory segmentation in 8086
If the external memory (1 MB) in 8086 based system is segmented into code, data, stack and extra which are all 64 kB, what do we do with the rest of the memory? Does it go waste?
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1answer
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Why ARM cores consumes relatively lower power than x86 [closed]
Why ARM cores consume little power compared with x86 CISC implementations?
What are the valid reasons?
because of it's fabrication technology?
Could this be right? ARM cores have been fabricated ...
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2answers
167 views
The modification of Instruction set [closed]
Recently I came to know that x86 instruction set can be regarded as obsolete. It should have been out of order a decade ago. Instead of being helpful, it can be called as burden. The only advantage of ...
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2answers
152 views
Can a disconnected pin on DDR3 SDRAM go undetected?
I was testing some DDR3 SODIMM modules using Memtest86+ on a Lenovo Thinkpad T520. I re-tested a module that I previously marked faulty and it came out fine.
So I wonder if it's possible that the ...
