All Questions
10 questions
1
vote
1
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107
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Struggling to understand how a JK flip flop can behave contrary to understanding
I have tried to understand how the JK flip flop in the image below (U3B) is behaving, and I am at a loss.
For context, I've included related parts of the circuit. However, to avoid muddling my issue, ...
- 139
2
votes
1
answer
5k
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Rising Edge vs Falling Edge D Flip-Flops
Is there any difference between a rising edge and a falling edge triggered D flip flop? For example, a falling edge flip flop will be faster or if there will be any change in result.
Is it correct for ...
- 21
0
votes
2
answers
2k
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Confusion about when a JK flip flop is triggered
I started learning about latches and flip flops recently, and my understanding is that edge-triggered devices like flip flops ignore their inputs until the clock signal transitions from low to high or ...
- 137
9
votes
1
answer
4k
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Is there an intuitive explanation of the classic edge-triggered flip flop circuit?
I figure there must be a way to understand it in terms of the three underlying latches somehow locking each other out, but I'm not getting it.
Is there a way to understand the edge-triggered flip ...
- 3,105
0
votes
0
answers
270
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Turn a positive clock edge into a negative pulse to make a 74LS170/670 register file synchronous
This is a follow-up o Why did they make the 74x170 (670) register file asychronous, no CLK input?.
I want to use that "register file" for my project, but I need to make it behave properly as a ...
- 1,669
0
votes
2
answers
203
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Low power dual edge detector using too much power
I am creating a hobby circuit which transfer signal to edge triggered pulses. I created circuit like this:
But I have issue with power consumption. XOR gate need power which take 8mA which is really ...
- 11
2
votes
3
answers
246
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Deciding which assembly is more common positive edge detector
I know of two circuits which can act as edge detector:
A clock connected as a voltage source across a RC component where resistance is composed of a diode and a resistor and this in series with ...
- 279
-3
votes
1
answer
1k
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How to implement a negative edge triggered D Flip Flop (Master Slave Configuration)?
Can you please post a picture of the implementation of such flip-flop at logic gate level? How can I easily change a positive edge triggered D Flip Flop to a negative edge? Also, how will the truth ...
- 1
3
votes
2
answers
4k
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Why is D flip-flop positive edge triggered instead of level triggered?
I'm trying to understand this D type positive edge flip-flop:
simulate this circuit – Schematic created using CircuitLab
I'm having problem understanding why it is positive edge triggered and ...
- 41
2
votes
1
answer
681
views
Reconize JK Flip-Flop operating edge: rising or falling?
This is a JK Flip-Flop image.
Using this image is there a way to know if the output changes on raising or falling clock? In other words, is input data
transferred to the outputs on the HIGH-to-LOW ...
- 210