Questions tagged [generic]

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Feature 'logo/labels' on cases of self made devices

Not really an electronics question however has something to do with the tech you have used for your own projects. For example, on any consumer device with USB support, Bluetooth, HDMI 2.x etc there is ...
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1answer
122 views

Using VHDL integer_vector for a block ram type, how to restrict the integer range?

Trying to simply infer block rams in a design with varying depths and widths. I'd like to have one ram definition since it is going to use a vendor specific attribute and it seems like a good idea to ...
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2answers
444 views

Verilog Generic Multiplexer - synthesis warning and simulation compile error using Xilinx ISE 14.7 "Port must not be declared to be an array"

I am pretty new to Verilog. I wrote a description for a generic multiplexer in Verilog as follows: ...
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1answer
208 views

Create array of std_logic_vector in VHDL with increasing bit-width based on generic parameter

I have following scenario I[n] = nth Data Input, where n=1 to N W = bit width of I[n] A[k] = output of a signed adder, where k = 1 to N-1 I want to use my signed ...
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1answer
147 views

VHDL unranged integer input ports bad practice?

I'm designing a customizeable interpolation filter and I'm looking for the best way to pass the coefficients (rather supporting points) to the filter. Below you see the current implementation. ...
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1answer
69 views

Antenna transmission when a generic signal is applied

In a basic course of Electromagnetic Field, we arrived to introduce antennas. We studied the behaviour of the antenna by computing the electric field created when a sinusoidal input (the current ...
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1answer
668 views

Xilinx ISE, expression not globally static inside generic map

Is this expression allowed inside Xilinx ISE: generic map (record1.field1'length) ?? Previously I have defined record: ...
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1answer
514 views

passing Synplify options from Lattice Diamond TCL code

I would like to pass, from the TCL file that is commanding the Diamond tool of Lattice, some options to the Synplify synthesis tool. E.g.: It is possible to set a value of the VHDL generic at ...
3
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1answer
2k views

VHDL Unconstrained port in a entity

I've a problem with the definition of an entity. I'm writing a wrapper that accepts several generic. Among these generic there are some boolean values that have the function to enable or disable the ...
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1answer
1k views

VHDL: Does VHDL allow enum to be passed to generic?

Is it true that one can pass boolean, integer and its subtypes as well as std_logic_vectors as generic to a VHDL entity? Does this list also include enum types, which is user defined i.e describe an ...