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Results tagged with fpga
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user 34938
A Field-Programmable Gate Array (FPGA) is a logic chip consisting of an array of programmable logic blocks and interconnects that is configured by the customer after manufacturing—hence "field-programmable".
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How do VHDL case statements scale when additional expressions are added?
I am using a case statement in VHDL where the expression is a 12 bit bus address and the output is a 32 bit data bus.
Here is my code:
process (iAPB_BUS_IN.pclk)
begin
if rising_edge(iAPB_BUS_IN …
- 803
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Does a signal need to be in a clocked process to be registered (VHDL)?
I understand that it is best practice to register the outputs of all modules; so, I want to do that. However, I'm unsure what exactly it means to register an output signal.
I.e. Do I have to include …
- 803
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When would AXI4Lite be a better choice than the APB bus?
I'm working on improving and cleaning up an already functional large FPGA design that has a 64 bit data bus. … Those on team AXI4Lite argue that many third party FPGA IP blocks use the AXI bus; on the opposing side colleagues suggest that the APB bus may use less resources (FFs and LUTs)--though I have not been …
- 803
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How is a signal physically routed in an FPGA?
My interpretation of how routing is done inside an FPGA is like the following diagram:
When I say signals, I meant to say CLBs
At each intersection of the blue and orange wires, there is a switch that … is set when the FPGA is programmed to connect the two wires, as illustrated in the picture by the "Connection Point" dot. …
- 803
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Is this BRAM being fully utilized if I use a different data width?
Background
I am using a Xilinx FPGA from the Kintek-7 family. The documentation for the memory resources can be found here. …
- 803