All Questions
Tagged with computer-architecture bus
11 questions
1
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2
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167
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Memory clock and Bus clock
The bus clock rate is how many times per second data is transferred from one component to another. If we consider DRAM DDR4-3200, the clock frequency of the RAM bus today can be 1600 MHz at the same ...
- 13
0
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1
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138
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Computers: How signals in the bus can travel in either direction [closed]
I'm reading J. Clark Scott's book But How Do It Know.
When he is describing registers and the bus he illustrates this at one point as five registers sequentially parallel-connected to a bus.
As you ...
- 103
0
votes
1
answer
127
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Can a pin to DDR4 be as thin as household tinfoil? (0.016 mm)
Edit: I think using the term "bus" might be wrong here. A "bus" needs to be large enough to facilitate an entire DDR4 stick's bandwidth to the Northbridge. The connection to each ...
- 223
-2
votes
1
answer
889
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Is bit stuffing done after 6 or 5 consecutive 1's? [closed]
I am learning computer architecture and organization. I have the following doubt.
I have read that in bit stuffing a 0 is inserted whenever 6 consecutive 1’s are encountered. However, it may be noted ...
- 375
0
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1
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1k
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How to calculate the bandwidth of a synchronous bus with overlap in bus transfer and reading next data?
I am working through problems in Saylor Academy's computer architecture course. I can't understand how this kind of problem is solved:
Consider a 32-bit synchronous bus with f = 125 Mhz, an 8 nsec ...
- 2,331
-2
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1
answer
75
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How does the north-bridge (or analogous hardware) route memory reads and writes? [closed]
I would be tempted to think that there is some kind of parallel cache-line kind of mechanism, that works on registers that are set by the north-bridge drivers. But then, most architectures only allow ...
- 141
4
votes
1
answer
753
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Microprocessor architecture bits vs bus sizes
I am ready following on this website:
"Another big difference between 32-bit processors and 64-bit processors is the maximum amount of memory (RAM) that is supported. 32-bit computers support a ...
- 1,489
3
votes
1
answer
133
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Why do we need 'R_out' in 2-BUS arch?
Given some abstract architecture of CPU:
Note that this CPU has 2-BUS. Why do we need the R_out and R_in? If I use Gra/Grb/Grc then obviousely I will need R_out. The Same for R_in when I use Sra/Srb/...
- 81
0
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1
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1k
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Confusion about "host bus controller" and "host bridge"
Below part is quoted from the book "Beyond BIOS".
Each host bridge is represented in EFI as a device handle that
contains a Device Path Protocol instance, and a protocol instance that
abstracts ...
- 1,212
25
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4
answers
7k
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Why do CPU's typically connect to only one bus?
I found a motherboard architecture here:
This looks to be the typical layout of motherboards. EDIT: Well, apparently it's not so typical anymore.
Why does the CPU connect to only 1 bus? That front-...
- 1,087
-2
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1
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1k
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Where is the control, address and data bus in a computer
So have been reading up on data buses, address buses and control buses and I understand what they do, but am confused about where they can physically be found. Some books/sites I have found state that ...
- 101