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Results tagged with vlsi
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user 237839
VLSI stands for Very Large Scale Integrated circuits, which at one time had meaning in context to the scale of integration. With the advent of modern processes with billions of transistors per design, it is used as a generic term to mean ICs in common usage.
3
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On understanding tradeoffs associated with pipeline depth
In Weste and Harris's CMOS VLSI Design, they write the following in the context of a discussion about how different levels of design abstraction interact but, to be clear, my question is about the specific …
- 51
2
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3
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Why does input threshold occur at the unique voltage at which both inverter MOSFETs are in s...
A relevant figure of merit for a CMOS inverter is the so-called input threshold voltage (no relationship to the threshold voltage of a given MOSFET) \$V_{inv}\$, defined as the voltage \$V_{in}\$ at w …
- 47.1k
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Why do we alternate directions between metal layers?
In their CMOS VLSI Design and in the context of a discussion about the initial stages of floorplanning/physical design, Weste and Harris write that
Another important decision during floorplanning is to …
- 1
0
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1
answer
197
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Why do two nonoverlapping phase completely obviate the possibility of hold time issues?
In Weste and Harris's CMOS VLSI Design, they write
In Section 10.2.5 we will see that flip-flops may experience hold-time failures if the system has too much clock skew, i.e., if one flip-flop triggers …
CommunityBot
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251
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On different well processes (reasons)
My textbook (Weste and Harris's CMOS VLSI Design) is trying to explain to me the difference between n-well, twin-well, and triple-well processes. …
- 1,219
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On different well processes (reasons)
Some of this is answered in Chapter 2.6 of Baker's CMOS Circuit Design, Layout, and Simulation:
a) He argues that a big reason for using twin-well even if you can't isolate the p-wells from one anothe …
- 1,219
1
vote
1
answer
184
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On DC transfer characteristics, logic levels, and the static discipline
One thing that's confused me ever since I started studying digital design is what it means when books say, roughly, that we can choose or define the input and output thresholds for a given circuit fam …
1
vote
2
answers
188
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Is there any problem with implementing a tristate buffer this way?
Consider the following implementation of an inverting tristate buffer in CMOS:
My textbook (Weste and Harris's CMOS VLSI Design) says that to implement a (noninverting) tristate buffer we should precede …
- 1,219
0
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2
answers
195
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How does the second flip-flop in a naive synchronizer "prevent a metastable state from propa...
In this very nice answer it's explained that, fundamentally, a two flip-flop synchronizer's basic operation is to prevent the propagation of a metastable state (effectively, an invalid logic level) fr …
- 174k
2
votes
1
answer
251
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Understanding the rigorous definition of hold time
Consider the attached from Weste and Harris's (WH) CMOS VLSI Design. I follow all of the discussion and definitions except for the hold time definition. …
- 19.3k
0
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1
answer
148
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Why do I need multiple segments to model the RC flight time of interconnect?
As an example of what I mean, consider the example below taken from Weste and Harris's CMOS VLSI Design. I emphasize that they choose to use two \$\Pi\$ segments on one of the paths. …
- 473k
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Does minimizing stages necessarily give best outcome when designing circuit under a delay co...
In the context of digital design, a common situation is to have to design a circuit for minimum energy under a delay constraint. Suppose a given circuit can be implemented with various stages. Is it n …
- 1,219
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2
answers
112
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Why do we need output isolation for power-gated blocks?
In their CMOS VLSI Design, Weste and Harris give the following discussion of power gating a block of logic:
I am in particular interested in understanding the need for output isolation here. …
- 17.1k
1
vote
1
answer
339
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On different well processes (fabrication process)
My textbook (Weste and Harris's CMOS VLSI Design) is trying to explain to me the nature of fabricating wells in the twin-well and triple-well processes. …
- 607
1
vote
1
answer
153
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Justification for equivalent gate capacitance simplification in digital circuits
Indeed, in their CMOS VLSI Design, Weste and Harris claim that
(1) It is convenient to view the gate capacitance as a single-terminal capacitor attached to the gate (with the other side not switching …
- 241