6
votes
Accepted
How do I observe a PLL's frequency tracking once the lock has been acquired?
how the output frequency tracks the input say for a step change in
input frequency
If you look at the control voltage into the VCO, its average value (ignoring ripple) is representative of the output ...
- 473k
6
votes
Accepted
Output Voltage Range of Op amps
Output source current is very limited:
And if you increase the resistor to \$10\text{ k}\Omega\$ and use a \$100\ \mu\text{A}\$ current source, you'd have to consider the high bias current: \$\approx ...
- 9,638
5
votes
Why doesn't this amplifier work?
I'm not going to deny that it took a while to understand this amplifier, but I think it should work.
I've made some annotations to the schematic to guide the explanation better.
First, the 1st stage ...
- 4,708
4
votes
Is Cadence unable to simulate AC to DC converters using simple full bridge rectifier?
It looks to me like you need to use the "earth" symbol somewhere so that 0 volts is defined. At the moment there doesn't appear to be an earth on your circuit but that might be because you've cut-off ...
- 473k
4
votes
How can I draw layout for 2 NMOS having different body potential?
In a bulk CMOS process there's only one P-substrate area so then you cannot make this circuit. All NMOS body contacts connect to the P-substrate and that is the only option.
If you have a triple well ...
- 81.4k
4
votes
Accepted
Is it possible to import CAD model files into LTspice?
LTspice cannot use 3D models - it has no 3D view.
LTspice cannot use the footprint - has no PCB layout.
LTspice might conceivably be able to use the symbol, but I don't know of any way to import just ...
- 73.6k
4
votes
Trying to implement a low-pass filter with a LNA as an op-amp
You have a 1uF decoupling capacitor at the input of your LNA. That's why you see a bandpass behavior.
This produces a zero that, in turn, produces a high pass response. Therefore, you have made an ...
- 4,708
3
votes
Does the capacitance values matter in a full wave voltage doubler?
The doubler is essentially two half-wave rectifiers. You can estimate the peak-to-peak ripple of the doubler from:
\$V_R = \frac{V_{IN(peak)}}{R_L\cdot f \cdot C}\$
Where f is the frequency (valid ...
3
votes
Accepted
LNA design question - series drain inductor
How is there any headroom for voltage gain when the DC drain voltage
of M2 is equal to Vdd?
Plenty of amplifiers have inductors tying drain or collector to Vcc - all it means is that the average ...
- 473k
3
votes
Fastest ALU architecture
Your ALU has 12 bit input, and 8 bit output, so it can easly be implemented as a look up table. 12 bit input means you need EPROM with 12 or more address lines. 4kB EPROM will do job. You can't do it ...
- 323
3
votes
Accepted
What is the meaning of "a" and "z" in capacitor value - Cadence Virtuoso
I would assume they are SI prefixes. In which case,
a would be atto or \$10^{-18}\$
z would ...
- 70.7k
3
votes
Cadance to Altium Conversion - Is it Hard?
I have performed this very conversion on multiple occasions. The conversion is the easy part, and Altium is able to pull in the design within a matter of minutes. The tedious part, however, is ...
- 21.6k
2
votes
How do I observe a PLL's frequency tracking once the lock has been acquired?
PLL's with XOR gate mixers have many characteristics.
1) capture ratio vs Loop BW and Capture time vs loop BW
- the former defines the ratio of the fo / Delta f which is related to Q of a BPF ...
- 148k
2
votes
How do I observe a PLL's frequency tracking once the lock has been acquired?
The best way to do this would be to simulate with a step change in frequency. If your circuit simulation tool does not have frequency generator sources that can step their frequency then you have to ...
- 57.9k
2
votes
Design of low current sensor from 50mA to 2A in a dc-dc buck converter
Yes, you can use a small current-sense resistor to get a voltage proportional to current.
However, consider the competing tradeoffs. You want this to drop as little voltage as possible to not effect ...
- 315k
2
votes
Accepted
Change of Gate-Source Voltage of a NMOS Transistor due to Temperature
The gate-source voltage of a MOS transistor changes because of two things. An increase of the threshold voltage and a decrease of mobility with increasing temperature.
Which effect dominates depends ...
- 8,275
2
votes
Accepted
PSPICE simulation of capacitor voltage and current disagrees with math
How do you account for the switch in your hand calculations?
Spice has to do that. There is no such thing as a discontinuity when you are trying to do a continuous time simulation. Unless specialized ...
- 8,546
2
votes
Implementing analog multiplexers in LTSpice and Cadence Virtuoso
Another solution is to use a behavioural source with table(), such as this:
table( V(ctl), 1, V(1), 2, V(2), ... )
where ...
- 21.8k
2
votes
How to create an OOK signal in ADS
If a pseudo-random bit sequence is acceptable (and normally this would be preferable to a truly random source or a pseudo-random source driven by the system random number generator), there are the ...
- 134k
2
votes
Peaks in XOR-XNOR Waveforms
The pulses you are seeing as "peaks when both inputs transition" is totally due to different time delays through the circuit the from either input to the output.
Logic chip manufacturers go to great ...
- 57.9k
2
votes
Accepted
Question about fingering
When you change the number of fingers indeed, in first order, the DC solution should not change. If it does then maybe something is wrong.
Some design kits might take edge effects into account so ...
- 81.4k
2
votes
sdf generation using prime time
You need to push your design through the synthesis flow to get path timing information and generate the SDF file. Synopsys flow includes Design Compiler (...
- 121
2
votes
Arranging multiple board files in single board file
I would ask the PCB shop to panelize the boards for me. They will know their preferred panel sizes and required spacing between boards on the panel.
- 60.7k
2
votes
Accepted
channel length in Cadence
They can be different.
Usually in logic circuits, the optimal size (for sped and power consumption) is to have all devices at minimum allowable channel length -- the widths may differ.
For analog ...
- 20.3k
2
votes
Cadence gain and phase margin
The STB main form in Virtuoso will produce eval errors for any negative or gain phase margin, the same is true if you use the PhaseMargin function in the calculator. In cases such as these, doing it ...
- 51
2
votes
Accepted
Multi-input NAND gate or Multiple 2-input NAND gates (VLSI design)
This depends on the process and area vs. speed trade-offs. Clearly, making a NAND5 using 5 p-FETs and 5 n-FETs would be the simplest in theory, but it might not be the most effective. For one thing, ...
- 58.3k
2
votes
Accepted
Op Amp design - open loop gain 73dB, closed loop gain -200dB
Your open loop gain has a phase of -180 deg. Your VIN+ and VIN- labels are reversed.
This is not a good way to measure AC open loop gain; in general you can't get a good bias point, although it seems ...
- 20.3k
2
votes
Accepted
What is this error on DRC Cadence layout
That's not an error, but rather an informational message. It's standard to include these with some rules decks, since you are immediately provided context (what rule deck, what version, etc) right in ...
- 20.6k
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