User SW.

6 votes

2 answers

4k views

why in some circuit there is use of bubble followed by bar?

asked Mar 11, 2014 at 6:33

5 votes

3 answers

41k views

Please explain the following Verilog code of a D flip flop?

asked Feb 3, 2014 at 6:56

3 votes

1 answer

1k views

Please explain the following integer constant used in verilog

asked Apr 28, 2014 at 5:36

2 votes

3 answers

5k views

How to remove this warning in Verilog?

asked May 10, 2015 at 13:30

1 vote

1 answer

246 views

How to check output after FPGA Implementation?

asked May 14, 2015 at 5:43

1 vote

1 answer

979 views

How to remove the below error when doing FPGA implementation of program that use RAM using Xilinx block generator?

asked Apr 18, 2015 at 13:36

1 vote

0 answers

1k views

what is the approach to design edge triggered d flip flop? [closed]

asked Jul 27, 2014 at 14:27

1 vote

3 answers

2k views

Is D flip flop can be combination circuit?

asked Jan 28, 2014 at 5:35

1 vote

2 answers

3k views

How to design a left shift register

asked Mar 9, 2014 at 10:51

0 votes

1 answer

2k views

What is the amplitude of output signal in below circuit?

asked Jan 30, 2014 at 4:49

0 votes

1 answer

2k views

What's the first step to learn Verilog coding to sort values?

asked Feb 8, 2014 at 6:25

0 votes

1 answer

551 views

Is it fine to have different number of input/output port in module and module instant in verilog?

asked May 10, 2014 at 4:29

0 votes

1 answer

3k views

How to design 4-bit comparator using the below described logic?

asked May 11, 2014 at 13:45

0 votes

1 answer

5k views

how to show the internal wire wave in verilog output?

asked May 17, 2014 at 5:07

0 votes

1 answer

3k views

I tried to wrote verilog code of 4-bit register with parallel load. But i failed. I am pasting code with output.Please identify whats wrong with it

asked May 21, 2014 at 9:05

0 votes

1 answer

10k views

What is wrong with following Verilog code where I am trying to pass a one-dimensional array?

asked Aug 30, 2014 at 6:52

0 votes

2 answers

5k views

how to define port in test bench?

asked Sep 1, 2014 at 13:47

0 votes

1 answer

905 views

How does Verilog code run when it finds positive edge of clock?

asked Sep 21, 2014 at 13:25

-1 votes

3 answers

2k views

Do $fopen and $fwrite works with FPGA implementation also?

asked Apr 20, 2015 at 10:24

-2 votes

1 answer

3k views

What are LUT (look up table)? [duplicate]

asked May 15, 2015 at 6:03

Stack Exchange Network

20 Questions

why in some circuit there is use of bubble followed by bar?

Please explain the following Verilog code of a D flip flop?

Please explain the following integer constant used in verilog

How to remove this warning in Verilog?

How to check output after FPGA Implementation?

How to remove the below error when doing FPGA implementation of program that use RAM using Xilinx block generator?

what is the approach to design edge triggered d flip flop? [closed]

Is D flip flop can be combination circuit?

How to design a left shift register

What is the amplitude of output signal in below circuit?

What's the first step to learn Verilog coding to sort values?

Is it fine to have different number of input/output port in module and module instant in verilog?

How to design 4-bit comparator using the below described logic?

how to show the internal wire wave in verilog output?

I tried to wrote verilog code of 4-bit register with parallel load. But i failed. I am pasting code with output.Please identify whats wrong with it

What is wrong with following Verilog code where I am trying to pass a one-dimensional array?

how to define port in test bench?

How does Verilog code run when it finds positive edge of clock?

Do $fopen and $fwrite works with FPGA implementation also?

What are LUT (look up table)? [duplicate]