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2 answers
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1-bit computing with true one-instruction set architecture

Even though MC14500B is considered as 1-bit computing where it accepts 1-bit data to perform operation, the instruction set itself consisted with 4-bit instruction which leads having 16 total ...
Muhammad Ikhwan Perwira's user avatar
0 votes
1 answer
294 views

How to implement the Instruction Set in Logisim

I have an assignment that requires me to build an 7-bit CPU. I’m done with implementing some of the requirements that includes 4 8-bit registers (the requirements say I have to store the parity bit), ...
maira's user avatar
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2 answers
307 views

How are `call` and `return` usually implemented in microarchitecture? [closed]

This is a follow-on from this question: Are `call` and `return` usually instructions in a modern ISA? I'd like to implement call and ...
Connor's user avatar
  • 399
3 votes
1 answer
323 views

Are `call` and `return` usually instructions in a modern ISA?

I've been working through the problems in a game based around building a Turing Complete machine. One of the final problems asks you to implement the call and ...
Connor's user avatar
  • 399
0 votes
1 answer
64 views

Designing instruction emulating swap on a MIPS ISA with only 2 registers

In a typical MIPS ISA, you have only 2 working registers. But you have a large number of ALU units. How to design an instruction to emulate swap?
Nidhi's user avatar
  • 87
2 votes
1 answer
1k views

How do you fit so many instructions on a 8-bit processor?

I will preface this that it is highly likely that I have misunderstood how Harvard architecture works, but I cannot understand how an 8-bit instruction set, say the ATmega128 for example, can contain ...
Lyndon Alcock's user avatar
0 votes
0 answers
144 views

What is the cost of increasing the number of register names?

Increasing the number of registers in a CPU, has the upside that more values can be kept in registers instead of having to spill to stack. It has some downsides, one of which is that more instruction ...
rwallace's user avatar
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4 votes
1 answer
2k views

Are processor instruction sets royalty free? (e.g. ARM v9, x86)

I asked a general question on Law SE with one example (ARM) and for that example, I was directed to What exactly does ARM sell to vendors?. I've read that QA that ARM sells actual core designs. I've ...
Martian2020's user avatar
10 votes
3 answers
2k views

How does an operating system or program detect the CPU model name? [closed]

What kind of binary compatibility is present for 2 processors sharing an Instruction Set?. I had asked a question on Computer Science Stack Exchange, to which I got an answer which said: As a trivial ...
Shashank V M's user avatar
  • 2,331
0 votes
0 answers
252 views

MU0 register transfer level organization by adding index register

Q. Write the MU0 register transfer level organization by adding index register. Give the control logic for the following instructions and explanations. LDA S,X ; A:=mem((S)+[X]) STA S,X ; mem((S)+[X])...
Reitwiec Shandilya's user avatar
1 vote
1 answer
87 views

Linkage pointer in procedure

https://ocw.mit.edu/courses/electrical-engineering-and-computer-science/6-004-computation-structures-spring-2017/c12/c12s3/procedures_answers.pdf I don't understand how the linkage pointer can be the ...
Ray's user avatar
  • 159
-3 votes
1 answer
1k views

What is the difference between Computer Organization and Computer Architecture?

I am still not getting a clear picture from any textbooks. Anyone, please elaborate with examples. What does 8086 architecture block diagram refer to?
Lelouch Yagami's user avatar
0 votes
0 answers
170 views

what were the ENIAC's equivalent to the modern CPU's elements?

If a modern CPU contains these elements: - 3 or more register units - ALU - control unit and the CPU is connected to a RAM composed of several addresses, what ...
Gigiux's user avatar
  • 113
-2 votes
1 answer
333 views

What is the difference in design between a von Neumann and the Harvard's machines?

Although there are many webpages talkink about the difference between the Aiken (prototype: Harvard Mark I) and von Neumann (prototype: ENIAC) architecture, the actual divergence remain uncertain to ...
Gigiux's user avatar
  • 113
0 votes
1 answer
247 views

Where in the instruction pipeline is machine code to microcode translation?

In my computer architecture courses on the N-stage pipeline, I never encountered the concept of microcode. I was surprised, then, when in a performance analysis course assignment, I discovered that ...
Dragonsheep's user avatar
-4 votes
1 answer
102 views

Where to study Cortex R architecture? [closed]

I am interested to study Cortex-R architecture but I cannot find its details online. Is it proprietary detail or should I ask for this information from arm.com? Obviously I am not looking for the ...
alt-rose's user avatar
  • 1,489
3 votes
3 answers
7k views

What is the role of ISA (Instruction Set Architecture) in the comp arch abstraction stack. [closed]

I have programming background, and I recently started taking computer architecture course. Most of the lectures I see use the some sort of the layering as described in the following diagram explaining ...
Vivek Maran's user avatar