All Questions
13 questions
2
votes
1
answer
345
views
VHDL FIFO w/ RAM
I've been tasked with designing a FIFO in VHDL for the block diagram below. I understand the general mechanism of how a simple FIFO works, but I've been struggling with how to connect the address from ...
-1
votes
2
answers
690
views
How to avoid empty FIFO when the read clk is higher than the write clk
I have an ADC, and, in order to avoid sync problems, I have used a FIFO with two different clocks: one for the write operation, that works at the ADC clock frequency and the other, FPGA clock that is ...
0
votes
1
answer
600
views
Writing into a full FIFO
I am using a FIFO as a temporary memory block to store values and then perform some calculations between the neighboring values once the FIFO becomes full. After the calculations are finished, I would ...
1
vote
2
answers
533
views
VHDL: ADC to USB Buffering using Fifo
I am trying to understand what is the correct way of doing such application, so please do not ask for complete code because each component is working fine on its own. I am struggling in the way of ...
1
vote
1
answer
2k
views
In digital logic, when given a requirement of a 64 byte FIFO, is it possible to calculate the width and depth?
I have an input device that can write in either serial, 8-bit parallel, or 16-bit parallel. I know the input frequency and max write speed of those data formats.
I am given a requirement of a "64 ...
1
vote
1
answer
1k
views
Problem FIFO in the implementation (VHDL)
I was working in that for the past five days and I don't know what happened. I must implement a FIFO to send some information, I attach the FIFO that I use. As you can see in the code, this FIFO using ...
0
votes
2
answers
4k
views
Is there a connection between circular buffer, FIFO and shift register?
I know that circular buffer and FIFO are similar but do not understand the difference that causes different terms to be used. How do these two compare with a shift register?
How do I know if I need ...
0
votes
1
answer
491
views
Unexpected behaviour in Altera clock crossing FIFO
As far as I am aware, in a FIFO as we keep reading it will eventually become empty i.e no more data inside and its output shall become 0x0. If we keep reading it after it has become empty, we shall ...
0
votes
1
answer
86
views
Xilinx Coregen FIFO as ZeroDelay model
My VHDL design contains a FIFO generated by Coregen from Vivado 15.3. I try to debug the design with a ZeroDelay simulation. But the core is not Zerodelay and makes short changes (much shorter that a ...
0
votes
1
answer
164
views
FIFO for spartan 3AN : no storage on board but ok in simulation
I made a FIFO using the Core Generator and I'm trying to implement a code that use it...
1) By putting the switch (T9) ON, I start transmitting some datas to my fifo (Here H-e-l-l-o for test)
2) By ...
0
votes
1
answer
692
views
FIFO in VHDL : ERROR:HDLParsers:3324
I'm programming a Spartan 3AN using ISE and I would like to implement a simple code that uses a Fifo :
When I push a button, a data is sent to the FIFO and when I push another button, the fifo is ...
0
votes
3
answers
1k
views
-1
votes
2
answers
15k
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