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When you use the async assign for the pulse, you will see the influence of unequal delays in the comparator as glitches in the output. Registering the compare signal hides this, allowing everything to settle down before the next clock edge. (This is guaranteed by the place-route tool if it says the path meets timing.) If, down the road, you have some reason ...


Comparators are relatively complex logic, with long carry chains. I'd recommend something like this: module downClockerTest(pulse, clk, reset); output reg pulse; reg [24:0] count; input clk, reset; always @(posedge clk or negedge reset) begin if(~reset) begin count <= 25'h0; pulse <= 1'd0; ...


Yes, there is "bouncing" — but in this context, we call them "glitches". The comparator (count > 26'd24999999) represents a rather large amount of combinatorial logic, and there's no chance that all paths through this logic (and the associated FPGA interconnect) will have exactly the same delay. Therefore, the output pulse will experience one or ...


In Quartus Prime ver. 18.1 it is possible to do: set_global_assignment -name SOURCE_TCL_SCRIPT_FILE pinout.tcl

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