All Questions
Tagged with computer-architecture assembly
25 questions
0
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2
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109
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1-bit computing with true one-instruction set architecture
Even though MC14500B is considered as 1-bit computing where it accepts 1-bit data to perform operation, the instruction set itself consisted with 4-bit instruction which leads having 16 total ...
3
votes
3
answers
357
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Is assembly microarchitecture dependent?
Many microarchitectures can implement a given digital system architecture. For example, and as Weste and Harris explain in their CMOS VLSI Design,
Digital VLSI design is often partitioned into five ...
- 1,219
1
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3
answers
940
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Why use bytes instead of words for offsets in 'lw' and 'sw' instructions?
In assembly language, there are instructions like 'lw' (load word) and 'lb' (load byte). Both of these instructions involve adding an offset to a base address. It seems counterintuitive, however, that ...
3
votes
1
answer
323
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Are `call` and `return` usually instructions in a modern ISA?
I've been working through the problems in a game based around building a Turing Complete machine.
One of the final problems asks you to implement the call and ...
- 399
0
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1
answer
64
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Designing instruction emulating swap on a MIPS ISA with only 2 registers
In a typical MIPS ISA, you have only 2 working registers. But you have a large number of ALU units.
How to design an instruction to emulate swap?
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3
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0
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372
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How to using JAL in RISCV in this example?
Write a "replace" function that replaces every character in the source string between the first occurrence of character "(" and the first following ")" with character &...
- 31
1
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2
answers
2k
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How is sll implemented in MIPS?
I don't understand how MIPS would implement the sll (shift left logical) instruction using the hardware present in its ALU as shown in the diagrams below. Would ...
- 548
10
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3
answers
2k
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How does an operating system or program detect the CPU model name? [closed]
What kind of binary compatibility is present for 2 processors sharing an Instruction Set?. I had asked a question on Computer Science Stack Exchange, to which I got an answer which said:
As a trivial ...
- 2,331
1
vote
1
answer
293
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Expression calculated at assembly time
I don't understand the explanation. Doesn't the assembler have to calculate 3 * 4 + 5 so it takes longer to execute? Also since 3 * 4 +5 has more characters why does it not take more storage?
From ...
- 159
-7
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2
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175
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What is DIP (dual inline package)? [closed]
I searched on the net, but couldn't understand what DIP is. Is it RAM?
2
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6
answers
3k
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what exactly is single cycle instruction architectures?
I got the following text from lab work 2 of CMU's computer architecture course. I am actually trying to do this lab myself out of own interests and I am in no way a student of CMU.
The machine has ...
- 123
-1
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2
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939
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Difference between MIPS and ARM datapaths [closed]
I have just learnt simplified five stage pipelined MIPS architecture in the class. I am reading other Instruction Set Architectures (ARM currently) and found some differences between ARM and MIPS. ...
- 113
1
vote
1
answer
717
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implementing direct addressing mode for a load instruction on a mips archtitecture
Given a Mips machine with 26 bit addresses and 32 bits data-paths, where the load instruction is as follows
|OPT code|rs|rd|immediate|
|6 bits |5 bits|5 bits|16 bits|
The OPT code is the ...
- 113
2
votes
3
answers
532
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Curious how does ALU addressing work like in Assembly code?
When writing assembly code, say R1 = R2 + R3, it is pretty easy to understand the addressing procedure because all registers are close to the ALU. But I find it hard to see how does the ALU go to the ...
- 201
1
vote
1
answer
17k
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Use of $at register in MIPS?
Register r1 or $at, is it's sole use in pseudoinstructions? If so, is this the sole solution to enable pseudoinstructions within the architecture?
- 125
1
vote
1
answer
1k
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5-stage pipelined implementation (RISC) of a microprocessor
I'm trying to solve two questions about a RISC 5-staged pipeline that is not exactly like MIPS found here (everything is included in this post).
Consider the non-pipelined implementation of a simple ...
- 139
0
votes
1
answer
899
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ISA efficiency code compaction and memory traffic
I'm having issues understanding this problem and am new to ISA's. Here's a problem with 3 questions and my biggest question is, what is supposed to happen? Specifically, the HLL Code at the bottom.
...
- 139
1
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2
answers
3k
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Average Cycles Per Instruction
We have two different computers with the same instruction set. There are three classes of instructions (A, B, and C) in the instruction set.
Computer M1 has a clock rate of 80 MHz and Computer M2 has ...
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2
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2k
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Programming microcontrollers in ASM or C & how it's done
Just to clarify on these topics:
If I were to program a microcontroller in ASM I would use an assembler, of course. The assembler would compile the code into opcodes (machine code?)(generally 1:1 ...
- 3,461
5
votes
3
answers
5k
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How can the number of clock cycles required to complete an instruction in a pipelined processor less than pipeline latency?
I am not new to computer architecture but I have only academic experience with micro-architecture implementation.
I have heard and read this many times but never really bothered to understand the ...
- 907
1
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3
answers
2k
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Is it true that copying is the most CPU intensive operation?
A mech engineer said that copying puts more load on the microprocessor than "other" operations (e.g. moving data or creating the same amount of new data). Is this true? Can you elaborate? I understand ...
- 1,724
1
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1
answer
31k
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How does the Store Word(SW) and Load Word(LW) instructions work, MIPS
The SW and LW instructions are defined as:
...
- 1,770
0
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1
answer
279
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Seeing how Instructions get Translated (Computer Architecture) [closed]
Little bit of a confusing question, also an x-post (Since it may be more suited here than SO). But anyways Im really looking for learning some low level programming. Thing is, Dev boards like Arduino/...
user3073
0
votes
1
answer
391
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Writing a method using MIPS code
I am trying to understand how convert C code to MIPS code and I have having trouble understanding why the stack pointer( $sp ) needs to be manipulated before and after the procedural code.Isn't the ...
- 1,770
2
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2
answers
2k
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MIPS Main Control Logic
In the Patterson & Hennessy book,
This is for these 4 instructions, if I need to implement instructions like andi, addi, ori, j, etc, do I add on to this table? Or do I do something else?
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