7
votes
What are good values for standard design rules (like clearance, trace width, etc.) in PCB design?
The below image is table 6-1 from the IPC-2221 standards. These are the minimum conductor spacings as a function of the voltage between two conductors, for various scenarios:
In my experience, these ...
- 16.4k
5
votes
Accepted
How can I prevent the DRC in KiCAD from checking my silkscreen layers?
You can set the violation severity in your "Board Setup" dialog. Change it to "Ignore" for the silkscreen items
- 4,772
4
votes
Do PCB routing vias require soldermask expansion?
You might leave them open if you want to use them as test-points.
- 4,668
4
votes
What are good values for standard design rules (like clearance, trace width, etc.) in PCB design?
The IPC (formally the Institute for Interconnecting and Packaging Electronic Circuits) standards discuss minimum trace spacing and trace widths for circuit boards. They contain a lot of great ...
- 1,557
3
votes
Accepted
KiCAD: "Footprint has no courtyard defined" using Arduino shield template
If you look at the other footprints on your photo, there's a thin white border around them. That's most probably the courtyard.
KiCAD uses that layer to check if two different footprints are ...
- 138
3
votes
KiCAD: "Footprint has no courtyard defined" using Arduino shield template
The courtyard is the area that the physical component will be in. This is defined in IC’s to make sure they won’t collide when you solder the components.
There’s a design rule check mark somewhere ...
- 594
3
votes
Do PCB routing vias require soldermask expansion?
I generally tent them all unless, as mentioned by Kyle B, they're test points.
3
votes
Altium Designer 17 DRC taking for ever
Start by selecting only the important rules that you want checked. The first step would be to ensure that you do not have an excessive number of rules set up in your ...
- 21.6k
3
votes
PCB design rule errors, but can't understand why
You've got a hole there with a copper ring around it: The blue ring.
It is actually too close to the next pin.
- 100k
3
votes
Room Definition error in Altium
Option 1: Don't delete the original auto-generated room. There's no reason you can't have two rooms overlapping. One to tell where to place the components, and one to use for defining rules.
Option 2:...
- 134k
3
votes
Kicad DRC Error "Footprint has no courtyard defined"
The "courtyard" is typically a magenta/purple/pink color in KiCAD, and is the X-Y profile of the device. So if this were say a horizontal potentiometer, the courtyard would show the base, ...
- 16.4k
3
votes
Kicad DRC Error "Footprint has no courtyard defined"
The courtyard marks an area around a component that you want to be kept clear of other components. KiCad will warn if component courtyards overlap.
If you don't have any components placed where they ...
- 60.7k
3
votes
Accepted
Ground Relief Gap Design Rule -- Altium
There are only specific built-in between-layer checks; you cannot create your own (e.g. by trying to query objects on a different layer).
You might be able to create your own via scripting, but that's ...
- 45.6k
2
votes
How can I allow shorts between the same net in Altium?
As others are mentioning, the Short Circuit DRC violation is likely appearing if the primitives you're working with are not actually on the same net. A good way to check this is by double clicking one ...
- 41
2
votes
Accepted
EAGLE - StopMask DRC Error
It's due to the fact that your reference designator font is "proportional", not "vector".
Proportional fonts in eagle are collision detected with a rectangular box which is what the DRC is erroring ...
- 70.7k
2
votes
Vias in a the layout of a CMOS Integrated Circuit
Since you are asking about VLSI design rather than PCB design we don't have to talk about the cost of the vias.
However, in current VLSI manufacturing the horizontal distance between features on the ...
- 31.7k
2
votes
Vias in a the layout of a CMOS Integrated Circuit
Excess would be the point where the board manufacturer replies saying it will cost extra to produce your PCB, as it costs them machine time drilling all those holes,
You can get pretty over the top ...
- 4,657
2
votes
Altium 20 Deleting Rules
In Project Options / Comparator set "Extra Rules" to "Ignore Differences". See image below:
- 21
2
votes
Altium - Hole to hole clearance rule that only applies when nets are not the same
Please see: https://bugcrunch.live.altium.com/#/idea/17603
For a requested Altium Designer feature (idea). It also lists some helpful work-arounds for the meantime.
- 21
2
votes
Accepted
Room Definition error in Altium
Rooms were used to keep components within or out of them.
If this room is not used for that, uncheck design > rules > ...
2
votes
Accepted
Altium: Component Clearance constraint won't go away after setting rule
You have another rule defined.
From your first image you can see the violated rule has the name "ComponentClearance" which I guess is set to match all objects.
Check your rules again for ...
- 46
2
votes
Accepted
What is this error on DRC Cadence layout
That's not an error, but rather an informational message. It's standard to include these with some rules decks, since you are immediately provided context (what rule deck, what version, etc) right in ...
- 20.6k
2
votes
Violations on USB connector in Altium
Just looks like you've got the tracks assigned a different net (or no net) from the pads so Altium is telling you they are shorted.
If you placed those tracks, remove them and replace them starting ...
2
votes
Accepted
A question about layout: How to connect the gate to metal 1 layer?
It depends on process details, but it's pretty common to not allow a metal to poly via on top of a transistor, no matter how wide the gate is.
The entire poly layer needs to get implanted, otherwise ...
- 1,526
2
votes
Define different clearance foriInternal and external layers in Altium
Right, so just include them in the query too. :)
Note that precedence matters, so, if those objects need to match multiple rules, those other rules should probably be earlier, and the objects queried ...
- 45.6k
1
vote
Accepted
Altium designer PCB - Strange and confusing symbols everywhere (From DRC - Design Rule Checker)
When you run the design rule checks, "DRC error/violation markers" are added to the PCB view, showing where objects violated one or more design rules.
The simplest way to clear them is to ...
- 34.9k
1
vote
Accepted
How can I limit design rules check on some components and its connected tracks in Altium?
From Altium Documentation:
https://www.altium.com/documentation/altium-designer/query-lang-pcbfunctions-objecttypechecks-ispolygonispolygon-ad
When defining an Electrical Clearance rule for polygon ...
- 401
1
vote
Vias in a the layout of a CMOS Integrated Circuit
regarding n-silicon use of vias ---- in a linear setup of vias, clearly the vias eat up part of the metal width, thus reducing the current-carrying ability.
I suggest you use wide metal over wide ...
- 35k
1
vote
Accepted
What factors do I need to consider when selecting an inductor to use in a circuit with the MT3608?
Consider the operation of this circuit. When the switch (SW) is "on," (tied to ground) the inductor has Vin across it, so the current in the inductor is increasing. Since \$V = L\times di/dt\$, you ...
- 11.8k
1
vote
Accepted
Altium rules help: keepout region around mounting point throws collision errors for the mounting point itself
I realize this is an old question and you've likely already solved it or moved on, but for anyone else that crosses this question: the reason DRC errors are being thrown is because you have set up the ...
- 156
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