Questions tagged [parasitic-capacitance]
Capacitance that arises from the physical layout of the circuit and the placement of components. Particularly notable when the addition of capacitance is undesirable.
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Capacitances in a PMOS transistor: what about the n-well?
So I'm studying MOS transistors and came across the topic of capacitances between various terminals/contacts, including the bulk terminal. These capacitances are due to lateral diffusion as a ...
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TPS61090 LBI Pin-->frequency compensating capacitor for voltage divider?
I was reverse-engineering some PCB to gain knowledge how to apply a TPS61090 Boost Converter (see my schematics attached, sorry for the unusual "arrangement" of the components). Input VBAT ...
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I2C bus fails after a few sensor reads
I'm building a small home automation hobby project for which I try to connect 4 temperature/humidity sensors (AM2320) to an I2C bus on the Raspberry Pi. When initially connecting the sensors they work ...
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Modelling an STM Tip current
As part of a current-to-voltage preamplifier that I'm working on improving, I'm trying to model the current source of an scanning tunneling microscope (STM). The way it works is described below (based ...
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Resistor-Capacitor-Resistor configuration and layout differences
How you can explain the R-C-R configuration? Goertz zobel
link to the web-article
This looks to be used as a RF audio cable terminating, I suppose.
Which can be the electro-technical difference of ...
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Plannar Inductor Unacounted Parasitic Capacitance
I'm trying to determine the source of approximately 300pf worth of parasitic capacitance in a planar coil project I'm working on. I'm trying to find out how my numerical predictions line up with the ...
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Why does op-amp output impedance / parasitic input capacitance pole cause a noise peak?
I was simulating the above circuit in LTspice... I realize the main problem here is the 2MHz peak (which should be fixable with proper compensation), but I'm curious about the smaller 398kHz peak ...
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Understanding spef format
Please help me to understand below scenario which is there inside the spef file. I have written only the snapshot, not the full text.
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What effect does the internal re-arrangement of charges have on the existing current? [duplicate]
In the figure, the circuit is physically isolated from Earth (The black line at the bottom). The red capacitors are parasitic capacitors.
Under switching conditions the node voltages relative to the ...
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Is this internal rearrangement of charges in a circuit a current and is this current different from the “normal” current of the circuit?
In the figure, the circuit is physically isolated from Earth (The black line at the bottom). The red capacitors are parasitic capacitors.
Under switching conditions the node voltages relative to the ...
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How much is parasitic capacitance of soldering pads on PCB?
I mounted a Resistor (SMD, Size: 0603, Resistance 500MOhm) on a PCB.
What is the value of its parasitic capacitance?
How would it change if it were 0402 in size?
Does it depend a lot on the ...
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Speedup capacitor for compensating stray capacitance
I may be wrong here but I think C1 and C2 charge to different polarities, so when the output changes, C2 supplies the required charge(+ or -) to C1 quickly.
For example: If the output is \$+V_{...
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What's the best procedure to model a real world transformer which is not so simple
I have a transformer with a 110-1 turns ratio.
The output winding (1100 turns) is typically open circuit, with only its parasitic capacitances as a load.
The output winding has adjacent turn ...
user121934
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I am trying to understand the behavior of a pulse
I have this pulse
This is the observed data. I have a LTSPice model that needs to be matched as close as possible to the observed data I need to match the e area of from 350 to 500 ns, because the ...
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Input and Output capacitance
I have understood that there are both input and output parasitic capacitances in real op-amps, but I am trying to understand why they are there.
As for the input capacitance, there are two types:
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Parasitic capacitance of a chip
I know that the parasitic capacitance of a chip is pronounced Cdyn.
If I apply on some scenario one the chip which will toggle the all of its transistors with two different voltages, but the frequency ...
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Understanding capacitance in oscilloscope probe tip
I am trying to understand the capacitance and resistance in oscilloscope probe tip.
In the above attached image, that 9Mohm resistance is used for that 1x and 10x setting that divides the input ...
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Measurement of Resistor Parasitics Inductance and Capacitance
I have seen people doing some measurements of parasitic capacitance and inductance of some resistors, by using a vector analyzer and analyzing the graph of S11 with respect to frequency.
To get this ...
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Perf board parasitic capacitance fries microcontroller?
Recently one of my mirocontrollers fried in a project on a perf board. Eight of the outputs are PWM, and aside from the power lines, there are no other outputs from the MCU. The PWM frequency is 40 ...
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MOSFET input and output capacitances
I need some explanations about the MOSFET parasitic capacitances. Precisely, what I studied is that there are those parasitic capacitances:
But generally in digital electronics texts I see that they ...
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Measuring parasitic capacitance of coil using an LCR meter
Would it possible to use an LCR meter (DE 5000) to measure the parasitic capacitance of an multi-tapped torid inductor?
If this is possible how should i do this, to get the best results?
Help is much ...
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Doesn't building a circuit "Manhattan-style" introduce lot of parasitic capacitance?
I watch a lot of circuit building videos on Youtube and I can see that the "Manhattan" style of circuit building (placing small islands of copper clad board on a larger piece which acts as the ground ...
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Under what conditions can power MOSFET gate capacitances Cgs and Cgd be paralleled?
I would like to get some understanding about the gate charge of a power MOSFET. I am referred to this MOSFET gate drive circuit application note:
On page 5, subsection 1.2.3, Gate charging mechanism, ...
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how to isolate coupled noise source in parasitic capacitance in high voltage pcb design?
I'm new designing a high/medium voltage (V <=10kV) with low voltage and low current (10mA). There will be only a few HV relays. Their coils will be triggered by LV.
I have read some literature ...
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Relaxation oscillator issue, comparator self-oscillating at 25 MHz (40ns propagation delay)
I have a relaxation oscillator circuit which is supposed to oscillate around 6 MHz. It mostly oscillates in a very stable manner around that frequency.
Sometimes, however, it starts to oscillate at 25 ...
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MOSFET Controled Relay Problem
As a way to power-on/-off a circuit load, a MCU is used to drive a relay through two MOSFETs. The problem is, when the MCU GPIO output is measured 0-volt, the relay could stay connected.
Can anybody ...
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Using only stray capacitance for MCU oscillator circuits
I've included a diagram of typical Pierce oscillator circuit taken from ST Application Note AN2867:
The note suggests that C_L1 and C_L2 should be chosen such that the following equation holds:
...
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Does (stray) capacitance depend on voltage?
While thinking about how to reduce stray capacitance on my pcb, I got triggered by the question:
Should the stray capacitance depend on the voltage difference?
Acccording to the equation of ...
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Spike in RTL Inverter
I do not understand the cause of this spike which can be observed in an RTL inverter (but also in a CMOS inverter). In the following image it is the peak at 10 mS (I have considered as input a signal ...
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Measurement of Cmos Parasitic capacitors
i've had a question which asks if we assume that capacitance of capacitors with w/l of 1u/0.5 are
then what are capacitance of capacitors (with the actual w/l)
now i know cgs in saturation for ...
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Measuring current vs voltage
Let's say that I have a periodic charge build-up across the capacitor C1.
I could either choose to measure the current using a transimpedance amplifier as shown below or could measure the voltage ...
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Electrical properties of a stack of strip board connected by through-hole pins/sockets
I'm aware that breadboards have a limit of 1-2MHz. I think this is because of capacitance.
Are there similar limits for a stack of stripboard connected by through-board sockets/pins? Would breaking ...
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Do MRI magnets oscillate due to parasitic capacitance?
Moved here from SE Physics.
Do MRI magnets oscillate during charging or even during persistant mode due to parasitic capacitance? What problems can this cause?
I am planning a low temp ...
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Tesla coil, where do the sparks from the secondary coil ground to?
This might be an obvious question, but I was wondering how a Tesla coil emits sparks that's seem to complete a circuit in thin air, and how one end of the secondary completes a circuit with the other ...
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What is the use of CC_to_GND option in starrc extract?
While doing parasitic extraction using starrc tool, I see there is a switch CC_ti_GND. It combines all the coupling caps and gives the cap with GND.
So my doubt is, in which case would it be useful ...
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Approximate Capacitance of a Multilayer Solenoid Coil
I'm interested in an expression for the capacitance or resonant frequency of a Helmholtz like coil (the windings are parallel to the plane of the coil) of circular or square cross section and of the ...
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Measuring Vackar Oscillator Output Amplitude and High Frequency Effects
This is somewhat related to my previous question regarding why I wasn't seeing a clamp biasing effect with my JFET Vackar oscillator. I think I figured it out and I'm wondering if you guys agree. ...
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How do the parasitic elements behave in a bidirectional power switch made from back-to-back MOSFETs?
I would like to know how to determine the value of the total internal gate mesh resistor (Rg) and different parasitic capacitors especially Cgs and feedback capacitor Cds of a bidirectional power ...
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Need help modelling the circuit with parasitic capacitance of a power supply in this scenario in SPICE
A single-ended source is connected to an inAmp of a data-acquisition board as follows:
As you see above, the shield is shielding the twisted shielded pair cable. The shield is tied only to the earth ...
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Calculating parasitic capacitance of serial zener diodes
simulate this circuit – Schematic created using CircuitLab
I have 2 series zener diodes like these in the schematic.
Their capacitance is C=225pF
How do I calculate their equivalent ...
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Parasitic capacitor current of an inductor
I am doing a double pulse test on SiC MOSFETs from 100-800 V and current from 20-80 A. The schematic is shown below (the values are not correct though):
In my first round of tests, I was getting a ...
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What will it happened when capacitance is almost the same as parasitic capacitance
I make a sample and hold (IC design),and it is combined with transmission gate and a 550fF capacitor,and my classmate told me that my capacitor is too small,almost the same as the parasitic ...
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Capacitive Voltage Divider and Discrepency in Output Signal
Background
I designed a capacitor voltage divider for the purpose of measuring the voltage step up of a resonator. Before I measure the voltage step up I wanted to measure the voltage divider ratio to ...
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PCB trace length
I have some doubts. At the output of my phono preamp there are very big coupling capacitors and i didn't have choice (i think so) - i had to make long traces with output signal. The trace width is 1....
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What order of magnitude should I expect the parasitic capacitance to be for a solderless breadboard?
I'm trying to account for some error in measurements for a circuit I have produced physically and simulated in spice. The only suspect seems to be the solderless breadboard as the error seems to ...
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Why do parasitic elements (e.g capacitance) appear on only high frequencies?
We know that the impedance of a capacitor is inversely proportional to the frequency then why is it not negligible when at higher frequencies ?
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PCB design Gnd copper pour near signal
im new to pcb design,im trying to add copper pour in my design ,I always seen PCBs with signal line between copper pour, but in my case copper pour is on one side since board width is 5mm only
just ...
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How is it possible that the reverse transfer capacitance of this FET is so low?
A FET has parasitic capacitance, which can be modeled as a capacitor between each of its terminals (gate, drain and source), which I refer to as Cgd, Cgs and Cds, as shown in the image below.
FET ...
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adjacent trace capacitance (horizontal)
I find a lot of online tools to calculate the capacitance between two traces (or a trace and a plane) on opposite pcb layers. One such tool can be found here: http://chemandy.com/calculators/...
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CML/LVDS driver for several GHz, parasitic RC filter formed by terminating resistance and load capacitance
Update:
Based on useful comments of The Photon, Andy aka and PlasmaHH.
As I got, there is indeed the parasitic low-pass. There is no magic bullet that will mitigate it. Large receiver capacitance is ...
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