Questions tagged [zynq]
Zynq is a range of programmable SoCs from Xilinx, that integrate an ARM-based processor and an FPGA fabric.
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How do I configure UART clock settings in vivado for the Zynq7 PS and make sure it is exported properly to hardware?
I want to modify the clocks in the zynq 7000 PS for a peripheral, e.g. the UART, so I can operate one of the UART's at a desired baud rate. I wanted to set the UART clock for 80MHz in the Zynq 7000 PS ...
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Interfacing high-speed ADC with ZYNQ 7020
I need to interface a high-speed ADC (100 Msps or higher data rate) with a ZYNQ 7020 core board, which has limited number of pins available to use (100 pins). I need to sample a 30 MHz signal with my ...
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Choosing DDR3 for Zynq-7000 (XC7Z010-1CLG400I)
Looking at the AC characteristics of the Zynq-7000 it is said that the maximum data rate of the -1 speed grade is 800Mbit/s (it is also specifically mentioned that the clock frequency for data ...
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ZYNQ FPGA Develope tool chain on mac
I have an Macbook m3, and a third party ZYNQ 7020 board. I understand that Xilinx doesn't support macos platform at this stage. but I wondering if anyone can show me an toolchain to develop PL and PS ...
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Simulating and verifying DDR3L clock
Context
I am working on a PCB that hosts a Zynq Ultrascale+ SoC and has 9 DDR3L SDRAMs (MT41K512M8DA) operating at 1866Mbps, and I have to verify the signal integrity of the DDR3L interface. I am ...
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What tool is required to implement data transfer between PS and PL of Zynq 7000 SoC?
I am new to embedded programming. I undetstand a little bit what Vivado and Petalinux does. But I would like to how exactly I can use Vivado and Petalinux to perform data transfer between ...
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DAC DDR Interface with Vivado and Zynq7000
i need to connect a dual-channel DAC (AD9117) to a Zynq 7000 FPGA. The DAC has a DDR Interface, on which the Data for Channel 1 is clocked on the rising edge and the data for channel 2 on the falling ...
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VHDL rising_edge on 1Hz GPS input
The FPGA project I am working on requires events within an FPGA to be triggered off a 1Hz PPS coming from a GPS module. I have sampled this pps and then tried implemented logic triggered by this ...
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How to use Zynq to program STM32 MCU?
I have a custom Zynq board. I need to use this board to program the STM32.
The binary of STM32 will be stored on the Zynq board. How can this be done?
I am assuming jtag/swd but not sure how to do it.
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Is it possible to use basic networking on an FPGA without an OS?
I need to set up networking (just a basic echo server) on an FPGA board (ZYNQ Ultrascale+) using only the PL side. The end goal is to DSP a large amount of data coming from a receiver through ethernet....
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Zynq PS_SRST pin is not connected in my design - can I still avoid locking the device down?
Unfortunately our board design is missing the PS_SRST pin connection on our Zynq XC7Z045 device - it is not connected (not pulled high or low). As a result the device is (apparently) entering lock ...
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vivado HLS or SDsoc for use openCV
I want to do an image processing by openCV on FPGA . But I do not know if I should use the SDsoc method or the vivadoHLS method. The size of the images I am going to process is large and I want to ...
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Power Consumption for DDR3L SDRAM IC's
Designing a board that will utilize some DDR3L memory for the first time and looking to gain some confidence in some steps I've assumed/taken so far.
I plan to use two 4Gb SDRAM IC's (MT41K256M16TW-...
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How many DDR memory chips can be connected to Zynq UltraScale+ MPSoC ZCU104
I have a question regarding Zynq UltraScale+ MPSoC: how many DDR RAMs can be connected to the ZU7EV device, including both PS and PL banks ?
Here is the link for TRM.
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JTAG ID to differentiate similar devices
Is there a reasonable way to identify different boards with the same parts through JTAG? I have a family of boards that all have the same Zynq CPU but various hardware configurations. I'd like to be ...
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Trying to use 5 registers in Xilinx's AXI Lite interface
I have an IP for Digilent's Zybo Z7-20 which segments the image. The segmentation is done based on histogram. The segmentation module takes 4 32-bit wide inputs which contain the threshold values. In ...
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Direct Access to Ethernet port via FPGA on Pynq-z2 board
I am using the pynq board for developing FPGA code for an application. For communication with the PC I am using the ethernet port given on the pynq board. By default the ethernet port is configured to ...
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How to encrypt Bitstream on RedPitaya board?
I have developed my own bitstream for the RedPitaya SDRlab 122-16.
I wonder if it is possible to encrypt the bitstream.
I already know that I need to set a .bin file including the software counterpart ...
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Xilinx Zynq7k 020 linux, error when compiling u-boot
I get the following errors when compiling u-boot (SoC Zynq7k 020)
What I did:
git clone https://github.com/Xilinx/u-boot-xlnx.git
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Zynq block design : beginner's questions [closed]
I am a beginner and trying to create a zynq block design using ZedBoard. I have added Zynq from IP catalogue and run it using Designer Assistance + connect two port (M_AXI_GPO_ACLK and FCLK_CLKO):
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Powering Zynq-7000 from 28VDC
I need to power a Zynq-7000 chip from a 28VDC bus. The chip requires a few different voltage rails, 3.3V being the highest and the core voltage of 1.0V being the lowest. Current will be approx. 2.5A ...
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How do I diagnose problems with serial port communication between a PC and a Blackboard?
I am trying to write an application that runs on a Blackboard and it is supposed to send/receive characters to/from the PC COM port. The application on the PC is Xilinx 'Visits Serial Terminal'.
In ...
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AXI Stream write and read not synchronized
Searching "hls axi dma" on this site gives a few related issues but none of which I can use to fully deduct a solution for my problem.
My code generates "random" output on IO1 and ...
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Changing the value of a PL SelectIO pin with the PS
Using the Zynq architecture,
Is there a way to tie a PL SelectIO pin directly to memory address shared by the PS and the PL ?
Let's say address 0x000FFFF holds a std:vector 0101
I want PL selectIO ...
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Vivado Zynq DMA unconnect automically generated AXI-Lite interface from AXI Interconnect?
I am trying to initiate a MM2S stream read from the programmable logic of a Zynq board. I have inserted the AXI DMA IP, and intend to use the AXI-Lite interface on it to program the registers in the ...
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AD7626 interfacing with Zynq or Kintex
I want to connect an AD7626 with a Zynq FPGA or a Kintex. Which bank should I choose?
Let say the for case
Chosen Zynq FPGA has only HR bank
Kintex has HR and HP bank.
How should I choose a bank ...
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Why is retimer circuit provided for HDMI TX lines?
I am exploring a Zynq ultrascale+MPSoC design. While looking at the reference design of XCZU9FFVB1156 SOC evaluation board, in the HDMI interface there is a retimer IC in the transmitter side of Bank ...
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Embedded system - copying data from flash to RAM
This question uses some Xilinx-specific terminology.
I'm currently working with a Zynq Ultrascale+ MPSoC (CPU + FPGA in same package). I'm using a QSPI flash chip to hold the CPU configuration code, ...
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Selection of fastest speed grade of Zynq in Vivado
I would like to make an implementation in Vivado using a Zynq z7030. I see that there are about 32 possible zynq's available. I would like to know which one of them is the fastest (if that can be said ...
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ADC conversion rate
I have an ADC which is part of the Zynq-7000 SoC. For details please see the attached datasheet. I need to asses whether this ADC is appropriate for my application (measurement of stator currents in ...
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How to control AXI DMA and/or BRAM cores in a ZYNQ
I am trying to produce a sine wave using the DAC of a ZYNQ board (red pitaya). It is important that I have accurate control over the phase of the signal that I am producing.
I would like to do this ...
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External clock with Arty Z7 FPGA development board
I have a digital audio source that is basically I2S. I need to run the FPGA at the exact clock as the I2S provides. I've got four such inputs required, but I am assuming that the clocks are the same.
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Software Driver for custom AXI-stream IP in Xilinx SDK
I created an IP (say 'myip') using HLS with AXI-stream input and output. After connecting the IP to Zynq and exporting the bitstream to SDK, header file xmyip.h got generated which had functions like "...
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How fast is L1 cache of ARM Cortex-A9 in Xilinx Zynq-7000 FPGA?
I consider writing a small program for the ARM Cortex-A9 in the Xilinx Zynq-7000 FPGA, so the program will be small enough to fit into the 32 KB L1 instruction cache. The data will also be less than ...
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Booting the processor on a Xilinx Zynq 7000 before the logic
I am testing some code on an Xilinx Zynq 7000 and I need to be sure that the processor will boot up before the logic does. After reading through some of the manual it seems that this may be the ...
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Why is 7:1 video serialization required?
I am trying to migrate portions of a ZYNQ design from one platform to another. Part of the project is based on Avnet's ALI3 touchscreen kit. From the docs:
The 7-inch Zed Touch Display Kit includes ...
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How does one change Vivado IP signal types?
The Xilinx IP block called Utility Buffer allows the designer to convert one single-ended signal to a differential signal pair (among other things).
However, the block expects the input and output ...
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gcc __attribute__ section not working?
I'm working on a Zynq Ultrascale+ MPSoC and trying to play around with the on and off chip memories. In the following program, I'm trying to place only variable 'x' into OCM (on-chip-memory) where ...
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Shared or separate SPI buses for peripherals in a PCB?
I have four SPI-controlled chips which I want to control from Zynq-7020 via an FMC LPC connector. Each chip/device requires an SCLK, MISO, MOSI and CS line.
I'd like to give each device their own ...
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Vivado: Reset signal flagged as primary clock by Timing Constraints Wizard?
I inherited an FPGA design (Avnet MicroZed PCB) that does not meet timing. I have found that many of the design constraints are missing, and I am in the process of trying to properly implement the ...
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How to increase memory on the FPGA board?
Situation
I'm running a driver code driver.cc on the FPGA board (PYNQ-Z1) but it gives an error in the middle of the code where the code calls to ...
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2D convolution on 32x32 grayscale image on FPGA using verilog for inference of CNN
I am new to the world of convolutional neural networks and would like to implement a 2D convolution operation using the sliding window approach on a xilinx FPGA. The input to the image is a 32x32 ...
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Vivado "Export hardware" packs unknown bitstream
We have a Zynq project in Vivado 2017.4. I can generate the bitstream, in proj/proj.runs/impl_1/mybitstream.bit.
Then I want to import that configuration to my ...
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Non-coaxial 50 ohm cable for LVDS
I'm looking to configure a Xilinx Zynq-7000 custom board with LVDS receivers according to the following diagram.
In my setup, the 'IOB' on the left represents an LVDS driver from a radar receiver and ...
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Xilinx ZYNQ/ARTIX7 Invert Clock without inducing skew
For HDL design I'm currently developing for a zynq SoC, I need to invert a clock signal because of a swapped differential pair on board level.
Using "NOT" to invert adds a LUT in the path and as ...
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Can a heatsink protect a PYNQ-Z1 board from damage? If so, which one should I use?
I'm going to purchase a PYNQ-Z1 FPGA development board from Digilent (Link: https://store.digilentinc.com/pynq-z1-python-productivity-for-zynq/). However, some of the comments on the linked page say ...
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Vivado Video IPs not working as expected
I've been trying to understand how to utilize AXI-Stream IPs for Video processing and display via VGA for a few days now, but can't seem to get any circuit to work. Here is a test circuit I created:
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Connect to Xilinx Zynq 7030 via JTAG connection?
Imagine you are trying to write Bare Metal applications on a Xilinx Zynq 7030 board.
Since burning sd cards all the time gets tiresome, you want to establish a JTAG connection. You get a JTAG HS3 ...
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Using Memory values in Verilog / VHDL
In Xilinx Vivado IP integrator, I want to create a custom building block. The block need to be able to access the memory space (possibly external RAM) by itself.
The target function of the block can ...
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HDMI (ADV7511) Output Design on Zynq zc702
I am relatively new to embedded systems, so please forgive my ignorance. I am attempting to build a hardware design in Vivado which supports console output on HDMI, using the Zynq ZC702 running ...
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