All Questions
Tagged with computer-architecture cpu
105 questions
7
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How does pipelined CPU access both code and data memory in real life?
In the Digital Design and Computer Architecture RISC-V Edition page 442, a pipelined CPU is designed with separate instruction and data memories, as shown in the figure below.
However, this picture ...
- 193
4
votes
1
answer
162
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Understading CPU pipeline stages
I'm working on implementing a CPU that needs a three-stage pipeline. The division of those stages is open for me to determine.
I am struggling to comprehend how the stages are counted. While some ...
- 75
0
votes
3
answers
148
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Single port ROM: how does the CPU read constant data?
I am looking at different CPU micro-architectures.
Frequently, it happens that the ROM is supposed to contain only instruction data. See below for an example:
In such design, how is the CPU supposed ...
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0
votes
1
answer
48
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Are iGPUs utilized in any way while using a discrete GPU? Could they? Should they?
Whenever I've seen die shots of CPUs that contain integrated GPUs, it seems that the GPU takes up a not-insignificant portion of the die.
(Source: AMD "Phoenix 2" die shot, purely an ...
- 103
0
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0
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40
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does data and instruction memory we see in the data path corresponds to the L1 Instruction and Data cache inside of the core?
In CPU data path there are blocks called data memory and instruction memory ? Are these blocks L1 Instruction and L1 data caches ?
For instance check figure 4.10 in this link.
We know that generally ...
0
votes
1
answer
294
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How to implement the Instruction Set in Logisim
I have an assignment that requires me to build an 7-bit CPU. I’m done with implementing some of the requirements that includes 4 8-bit registers (the requirements say I have to store the parity bit), ...
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3
votes
1
answer
140
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Why forward from MEM Stage in a sequence of add instructions that all contain the same register?
I was reading Computer Architecture and Organization 5th edition by Patterson and Hennessy. In Chapter 4, section 4.7 on Data Hazards, I read the following excerpt regarding forwarding from the MEM ...
5
votes
6
answers
751
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Were vacuum tube computers made of logic gates?
A lot of introductory resources on modern CPU present them as being built from NAND gates (see here and there for instance).
Actually, it is possible to build a modern CPU using almost exclusively ...
- 187
1
vote
0
answers
53
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Wrong value in memory because of a branch misprediction
Lets say we have instructions like:
bne r1 $0 loop
sw r2 0(r1)
Let's say we go ahead with the taken path, i.e., execute the sw instruction after bne assuming the ...
0
votes
1
answer
92
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Is it possible to make the "arithmetic" part of the ALU to be mircoprogrammed?
We know that the Arithmetic and Logic Unit in CPU is a hardware, it is a combinational circuit. Binary addition, for example, is very fast because it doesn't have to be microprogrammed; there is ...
- 453
4
votes
2
answers
525
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How does CPU's Machine Check Architecture work?
Modern CPUs can alert the OS when itself is malfunctioning, i.e. logically incorrect, and apparently, this is supported by a hardware diagnostic feature called Machine Check Architecture. I can ...
0
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0
answers
118
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Mark Horowitz Computing's energy problem - methodology
I have a question about the Mark Horowitz paper: Computing’s Energy Problem
(and what we can do about it). In the paper, the author breaks down the sources of energy loss in modern computing systems.
...
- 41
0
votes
0
answers
45
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Can we service another memory request from L1 cache when an L1 miss is being serviced from L2?
Consider the case where L1 cache miss occurred and is being serviced by L2 cache which could take many cycles (may go to main memory in case of L2 cache miss). In the meantime L1 cache is idle, in ...
- 147
1
vote
1
answer
232
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Mitigating structural hazards in register files in processor pipelines
I am reading about structural hazards in pipelined architecture in processors. In classic RISC pipeline one such hazard is when we write and read simultaneously to same register, which may cause ...
- 2,782
3
votes
4
answers
845
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Is there any difference between a CPU core and a CPU itself?
I was reading this article that explains the difference between a thread and a core and it says the following:
...
- 889
4
votes
3
answers
2k
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How to do signed 16-bit arithmetic on an 8-bit processor?
For example, to add two 16-bit numbers on my 8 bit machine, I add the low bytes together, then the high bytes together, and then add the carry flag to the high byte of the output.
This strategy falls ...
- 139
2
votes
1
answer
569
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Program counter updating in a single-cycle ARM processor
This picture is from the book Digital Design and Computer Architecture: ARM Edition. It implements the LDR instruction.
I have one question:
R15 is supposed to be PC+8. In the picture, is R15 ...
- 299
0
votes
1
answer
2k
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How do computer memories interact with each other (registers, cache, RAM, ROM)?
After Googling around for some time, I have managed to get a good understanding what makes these components different, but I've yet to find any clear computer architecture-focused article/thread on ...
- 103
0
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1
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56
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Does the memory bus span multiple layers on die?
My question is if you take any model desktop CPU such as the ones manufactured by Intel would the design of the memory bus span multiple layers of a single die or would it be contained on a single ...
- 11
1
vote
0
answers
41
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Are coarse-grained reconfigurable architectures a subset of dataflow architecture?
By definition, dataflow architectures consist of large modules in the dataflow path, such as adders and multipliers for integer, floating-point, or fixed-point computation.
Hence, are coarse-grained ...
- 66
0
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0
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144
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What is the cost of increasing the number of register names?
Increasing the number of registers in a CPU, has the upside that more values can be kept in registers instead of having to spill to stack. It has some downsides, one of which is that more instruction ...
- 563
0
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2
answers
393
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Transistors collector input output of other transistor?
I'm new to computer science and trying to learn the basics. Have learnt how to create logical gates using simple components like relays, thanks to nandgame.com. This was easy, boolean functions, have ...
Timeless
2
votes
1
answer
194
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Internal differences between CPUs of the same architecture
What is the difference between, for example an Intel i3-4005U (1.7 GHz) and an Intel i3-4025U (1.9 GHz)? These CPUs are from the same generation, have the same amount of cores, cache, iGPU, and ...
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3
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What is the difference between stalling and flushing in a microprocessor?
As the title suggests, I want to understand the difference. Attaching the reference.
- 107
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1
answer
1k
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Is it true that CISC architectures generally consume more power than RISC architectures?
I keep hearing CISC architectures consume more power than RISC architectures. This is said to be the reason for using RISC architectures for low-power applications. I am a skeptic, I think it could be ...
- 2,331
10
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3
answers
2k
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How does an operating system or program detect the CPU model name? [closed]
What kind of binary compatibility is present for 2 processors sharing an Instruction Set?. I had asked a question on Computer Science Stack Exchange, to which I got an answer which said:
As a trivial ...
- 2,331
1
vote
1
answer
588
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Where is the RAM stored on a RISC-V CPU? [closed]
Does RISC-V have any opinion on whether the RAM is stored on the same chip as the CPU (like on ARM devices) or on a separate chip somewhere on the motherboard (like on an x86 desktop)? I assume that ...
- 125
4
votes
1
answer
406
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Why can't an Asynchronous CPU use a simple "completion bit" to signal completion?
I've been reading about how asynchronous CPUs work, but they always seem to involve some complicated way of communication. Wikipedia talks about a two-way and four-way handshake. I found a pdf from ...
- 1,087
2
votes
1
answer
157
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Size of a memory cache
Assuming we have a virtual address issued by a model CPU that contains a total of 32 bits and 20 bits of this address are reserved for the tag + the cache comprises a total of 1024 cache lines.
Should ...
- 227
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1
answer
2k
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Logisim: Implementing a control unit for "Addition", "Logic bitwise AND" and "right logic shift" in ALU [closed]
I'm very new to circuit design. I've built an ALU and now I only need a control unit for three operations, "Addition", "Logic bitwise AND" and "right logic shift". What ...
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3
votes
2
answers
400
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How can I fix delay between Instruction and Program Counter?
I am designing the MIPS processor, this includes Data Memory and Instruction memory for testing.
I had a problem with IM synthesis covered in this question (How to make a synthesizable Instruction ...
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-1
votes
2
answers
182
views
What is the most important CPU price factor [closed]
I have two intel CPUS with distinct features.
intel i7 8550U
intel i5 8300H
Which have big performance difference with the cheaper 8300H being higher in memory ...
- 99
1
vote
0
answers
61
views
Difficulty in understanding the concept of operand forward in pipeling and when to use split phase
Given below is a question from \$\text{GATE } 2015 \text{ CS}\$ paper,
Consider the sequence of machine instruction given below:
\begin{array}{ll} \text{MUL} & \text{R5, R0, R1} \\ \text{DIV} &...
- 155
4
votes
1
answer
802
views
Is it possible to remove the write back stage in 5-stage pipeline?
In this graph, can we simply remove the write back stage since the mux is pushed back into the memory access stage and there is no logic in the write back stage. Is it because of the register file ...
- 113
1
vote
4
answers
3k
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Can an FPGA/ASIC have an operating system?
I know FPGA/ASIC are for a specific task and they are not microprocessors and an OS is needed mainly if multiple processes (tasks) need to be run concurrently.
Just wondering if an FPGA/ASIC can have ...
- 93
1
vote
2
answers
468
views
What does the 8086 CPU do with the data returned from an address in RAM?
I understand how a CPU works fairly well, but there is this one thing which I've never really gotten the hang of.
Say we have an Intel 8086 CPU (16 bits wide registers) which is about to fetch its ...
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votes
1
answer
271
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A computer architecture joke [closed]
Background
Some months ago, I watched a Youtube video posted by the channel Numberphile. The video was on famous world mathematician Terence Tao, and in the video, he seemed to be struggling with ...
- 101
1
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1
answer
2k
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How can I modify single-cycle MIPS processor to implement jal command?
Hello Stack exchange community
I was wondering which modification should I have to make in order to enable single-cycle MIPS processor to run a jal(jump and link) command?
My most pressing confusion ...
- 11
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votes
5
answers
792
views
What are the disadvantages of CISC architecture?
I took the computer architecture exam today. Our teacher asked a question.
What are the disadvantages of CISC architecture ?
Increases the number of commands while writing the program
Makes ...
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1
vote
1
answer
114
views
electrification of all transistors
We discussed a topic in the computer organization course. The professor told us that when the computer first turned on, all the transistors on the CPU are instantly electrified. So he said, keeping ...
- 13
0
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0
answers
170
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what were the ENIAC's equivalent to the modern CPU's elements?
If a modern CPU contains these elements:
- 3 or more register units
- ALU
- control unit
and the CPU is connected to a RAM composed of several addresses, what ...
- 113
1
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0
answers
599
views
How to cascade IC 74HC161 correctly?
Currently I have this 4 bit CPU as shown in the schematic diagram below.
What I wish to achieve:
Add one more output register to make the CPU output a total of 8 bits
Show alphabet using the 8 bits ...
- 11
1
vote
1
answer
943
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Do 64-bit CPUs consume more power than 32-bit ones?
In this lecture about efficient computing for deep learning, the benchmarks show a 3-fold increase in power usage between 8-bit and 32-bit addition operations. Between 8-bit and 32-bit multiplication, ...
- 119
1
vote
0
answers
72
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Cache Memory Read and Write Miss/hit policies: details of a real processor
All the references I have checked so far explain the Read Miss,Write Hit/Miss policies at the same level of detail. I understand their concepts but I am looking for more details on their ...
- 13
1
vote
5
answers
314
views
Has a CPU with Highlevel language (C/C++) as machine code ever been designed?
I got a question popping directly from reading Tanenbaum's Structured Computer Organization.
Stating from Chap. 1 Sec. 1.1 :
A machine with C++ or COBOL as its machine language would be complex ...
- 337
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1
answer
521
views
5
votes
2
answers
332
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Thoughts & questions on custom CPU architecture
I'm designing a CPU architecture. I've come up with a preliminary design:
I'd like general thoughts on what I can improve in the design and also I have some specific questions:
Is it overkill to ...
- 155
2
votes
1
answer
2k
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The accurate time latency for 'lw' instruction in a single-cycle datapath
I want to calculate the cycle time of a single-cycle datapath. Then from the course, I know the time should be the execution time of the longest instruction, which is 'lw' in MIPS.
So I try to ...
- 21
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vote
1
answer
93
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CPU cache write policy - evict already dirty? + storage of memory address
I'm reading about cache in wiki https://en.m.wikipedia.org/wiki/CPU_cache and the following phrase seems not clear.
Also, a write to a main memory location that is not yet mapped in a write-back ...
- 113
0
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1
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372
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What kind of hardware multiplier do modern processors use?
I was wondering what kind of multiplier implementations modern processors use. Is it some derived variant of booth Wallace tree algorithm? Are these kinds of micro-architectural details publicized ...
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